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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, RECONF, IPSJ-ARC [detail] 2024-06-10
16:20		 Yamanashi Isawa View Hotel
(Primary: On-site, Secondary: Online)		 Rapid Inter-Thread Communication Using Message Passing Unit in RISC-V SMT Processor
Go Akamatsu, Shogo Takata, Tomoaki Tanaka, Hironori Nakajo (TUAT) 		 [more]
RECONF 2023-09-14
16:40		 Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)		 Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism
Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-24		 Vector processors can load lots of data and perform operations in parallel.
The Vector Register Sharing Mechanism, prop... [more]		 RECONF2023-24
pp.18-19
RECONF 2023-09-15
13:25		 Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)		 Implementation and Evaluation of a Hardware Accelerator via Vector Register Sharing Mechanism for Massive Data Transfer
Michiya Kato, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi MIyoshi (Wasarabo LLC), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-29		 Vector Register Sharing Mechanism is a method of data transfer by connecting some of the vector registers in the vector ... [more] RECONF2023-29
pp.40-45
RECONF 2022-06-07
14:50		 Ibaraki CCS, Univ. of Tsukuba
(Primary: On-site, Secondary: Online)		 Vector Register Sharing Mechanism for Hardware Acceleration
Tomoaki Tanaka, Ryousuke Higashi (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2022-5		 In this paper, we present a vector register sharing mechanism that directly shares vector registers inside the processor... [more] RECONF2022-5
pp.26-31
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-24
14:50		 Online Online Implementation of a RISC-V SMT Core in Virtual Engine Architecture
Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65		 The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been... [more] VLD2021-57 CPSY2021-26 RECONF2021-65
pp.43-48
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