Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
EE |
2016-11-28 13:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Poster Presentation]
Study of Ultra-low voltage oscillator for Energy Harvesting Satoshi Hashimoto, Tsutomu Yoshimura, Takao Kihara, Hiroshi Makino, Shuhei Iwade (Osaka Tech), Yoshio Matsuda (Kanazawa Univ.) EE2016-35 |
Recently, the energy harvesting such as the power generation with the electromagnetic wave energy and the thermoelectric... [more] |
EE2016-35 pp.29-33 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:30 |
Oita |
B-ConPlaza |
The LSI Implementation of a Memory Based Field Programmable Device for MCU Peripherals Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Hiroshi Makino (OIT), Kazutami Arimoto (Okayama Prefectural Univ.) VLD2014-108 DC2014-62 |
A Field Programmable Sequencer and Memory (FPSM), which is an embedded memory based programmable device for peripherals ... [more] |
VLD2014-108 DC2014-62 pp.239-244 |
IE, ICD, VLD, IPSJ-SLDM [detail] |
2013-10-07 10:30 |
Aomori |
|
A Memory Based Filed Programmable Device for Energy saving MCUs Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) VLD2013-46 ICD2013-70 IE2013-46 |
A Field Programmable Sequencer and memory (FPSM), which is an embedded memory based programmable peripherals for Micro C... [more] |
VLD2013-46 ICD2013-70 IE2013-46 pp.1-6 |
ICD |
2012-12-17 15:55 |
Tokyo |
Tokyo Tech Front |
[Poster Presentation]
A New Approach of the Analysis of the ISF in Oscillators with a Closed-Loop Control Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2012-97 |
The derivation of the impulse sensitivity function (ISF) of oscillators are widely used for the evaluation of the phase ... [more] |
ICD2012-97 pp.37-40 |
ICD |
2012-12-17 15:55 |
Tokyo |
Tokyo Tech Front |
[Poster Presentation]
Analysis of the Pull-in Range in a CDR-PLL with the Nonlinearity of the Phase Detector Shinji Shimizu, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2012-100 |
The analysis of the lock-in process of CDR-PLLs using the nonlinear model of the phase detector is presented. The analys... [more] |
ICD2012-100 pp.45-48 |
ICD |
2011-12-15 16:10 |
Osaka |
|
[Poster Presentation]
The design of TDC and ADPLL circuits considering metastable operations Yasuyuki Shimizu (Osaka Inst. Tech.), Giichi Sakemi, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2011-104 |
[more] |
ICD2011-104 pp.25-27 |
ICD |
2011-12-15 16:10 |
Osaka |
|
[Poster Presentation]
Simulation and Analysis of the Interference Noise between PLL circuits. Ken Maruhashi, Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (Osaka Inst. Tech.), Yoshio Matsuda (Kanazawa Univ.) ICD2011-110 |
When the multiple PLL circuits are laid out on a single IC chip, the influence of the interference between PLL circuits ... [more] |
ICD2011-110 pp.57-58 |
ICD |
2010-12-16 15:10 |
Tokyo |
RCAST, Univ. of Tokyo |
[Poster Presentation]
A Study of Pull-in Lock Simulation in CDR-PLL Yasuyuki Shimizu (Osaka Inst. Tech.), Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2010-107 |
[more] |
ICD2010-107 p.71 |
ICD |
2010-12-16 15:10 |
Tokyo |
RCAST, Univ. of Tokyo |
[Poster Presentation]
Comparison and Analysis of the Noise Sensitivity between LC-tank and Ring-type VCO Ken Maruhashi, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (Osaka Inst. Tech.), Yoshio Matsuda (Kanazawa Univ.) ICD2010-108 |
[more] |
ICD2010-108 p.73 |
ICD |
2008-12-12 16:35 |
Tokyo |
Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan |
Post-Silicon Programmed Body-Biasing Platform Suppressing Device Variability in 45 nm CMOS Technology Issei Kashima, Hiroaki Suzuki, Masanori Kurimoto (Renesas Technology Corp), Tadao Yamanaka (Renesas Design), Hidehiro Takata (Renesas Technology Corp), Hiroshi Makino (Osaka Institute of Tech), Hirofumi Shinohara (Renesas Technology Corp) ICD2008-128 |
The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technolog... [more] |
ICD2008-128 pp.137-142 |
ICD, SDM |
2007-08-24 08:55 |
Hokkaido |
Kitami Institute of Technology |
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variation in SoCs Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura (Kobe Univ.), Rei Akiyama (Renesas Design), Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata (Renesas Technology), Makoto Nagata (Kobe Univ.) SDM2007-156 ICD2007-84 |
Fine-grained built-in probing circuits are distributed at 120 locations on the SoC to allow continuous-time monitoring o... [more] |
SDM2007-156 ICD2007-84 pp.85-90 |
ICD, SDM |
2007-08-24 16:05 |
Hokkaido |
Kitami Institute of Technology |
A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial) SDM2007-168 ICD2007-96 |
We propose a new 2port SRAM with a 8T single-read-bitline (SRBL) memory cell for 45nm SOCs. Access time tends to be slow... [more] |
SDM2007-168 ICD2007-96 pp.145-148 |
ICD |
2007-04-13 09:40 |
Oita |
|
[Invited Talk]
A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) ICD2007-11 |
We propose a Wafer Level Burn-In (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair s... [more] |
ICD2007-11 pp.59-64 |
ICD, SDM |
2006-08-18 12:05 |
Hokkaido |
Hokkaido University |
A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stabi... [more] |
SDM2006-148 ICD2006-102 pp.133-136 |
ICD, SDM |
2006-08-18 14:35 |
Hokkaido |
Hokkaido University |
A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits Makoto Yabuuchi, Shigeki Ohbayashi, Koji Nii, Yasumasa Tsukamoto (Renesas Technology), Susumu Imaoka (Renesas Design), Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Hiroshi Makino, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] |
SDM2006-151 ICD2006-105 pp.149-153 |
ICD |
2006-04-14 13:50 |
Oita |
Oita University |
Worst-Case Ananlysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth Variability Yasumasa Tsukamoto, Koji Nii (Renesas Technology), Susumu Imaoka (Renesas Design), Yuji Oda (Shikino High-Tech.), Shigeki Ohbayashi, Makoto Yabuuchi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] |
ICD2006-18 pp.97-102 |
|