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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, CPSY, CAS | 2017-12-14 15:10 |
Okinawa | Art Hotel Ishigakijima | Accelerated Transient Analysis of Power MOSFETs by the Matrix Exponential Method Tatsuya Kamei, Shigetaka Kumashiro, Kazutoshi Kobayashi (KIT)  CAS2017-87 ICD2017-75 CPSY2017-84 |
In designing and developing power devices, reduction of simulation time is required. In this study, an accurate metric f... [more] | CAS2017-87 ICD2017-75 CPSY2017-84 pp.107-112 |
| SDM | 2017-11-10 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
An Accurate Metric to Control Time Step of Transient Device Simulation by Matrix Exponential Method Shigetaka Kumashiro, Tatsuya Kamei, Akira Hiroki, Kazutoshi Kobayashi (KIT) SDM2017-70 |
An accurate metric for the time step control in the power device transient simulation is proposed. This metric contains ... [more] | SDM2017-70 pp.47-52 |
| ICD, ITE-IST | 2011-07-22 10:25 |
Hiroshima | Hiroshima Institute of Technology | Analysis Methods of Substrate Sensitivity in an Analog Circiut Satoshi Takaya, Yoji Bando (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2011-28 |
Substrate noise sensitivity of an analog circuit consists of the sensitivity of a device and noise propagation from the ... [more] | ICD2011-28 pp.73-78 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 11:20 |
Fukuoka | Kyushu University | A Consideration of Substrate Noise Sensitivity of Analog Elements Satoshi Takaya, Yoji Bando, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) CPM2010-126 ICD2010-85 |
Measure substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 32 different geometor... [more] | CPM2010-126 ICD2010-85 pp.13-17 |
| SDM | 2010-11-12 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Modeling of Single-Event-Transient Pulse Generation in Inverter Cells Katsuhiko Tanaka, Hideyuki Nakamura, Taiki Uemura, Kan Takeuchi, Toshikazu Fukuda, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete) SDM2010-180 |
Soft errors in logic circuits due to the propagation of erroneous signal caused by ionized particle generated by cosmic ... [more] | SDM2010-180 pp.47-52 |
| ICD, ITE-IST | 2010-07-22 10:20 |
Osaka | Josho Gakuen Osaka Center | In-situ Evaluation of Vth and AC Gain of 90 nm CMOS Differential Pair Transistors Yoji Bando, Satoshi Takaya, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2010-23 |
[more] | ICD2010-23 pp.11-14 |
| SDM | 2009-11-13 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Discrete Surface Potential Model which Accurately Reflects Channel Doping Profile and its Application to Ultra-Fast Analysis of Random Dopant Fluctuation Hironori Sakamoto, Hiroshi Arimoto, Hiroo Masuda, Satoshi Funayama, Shigetaka Kumashiro (MIRAI-Selete) SDM2009-148 |
[more] | SDM2009-148 pp.73-78 |
| ICD, SDM | 2006-08-17 10:55 |
Hokkaido | Hokkaido University | A 1-ps resolution on-chip sampling oscilloscope with 64:1 tunable sampling range based on ramp waveform division scheme Kenichi Inagaki (Univ. of Tokyo), Danardono Dwi Antono (SONY), Makoto Takamiya (Univ. of Tokyo), Shigetaka Kumashiro (NEC Electronics), Takayasu Sakurai (Univ. of Tokyo) |
An on-chip sampling oscilloscope with 1ps timing resolution is realized in 90nm CMOS process based on a proposed ramp wa... [more] | SDM2006-129 ICD2006-83 pp.25-30 |
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