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| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-17 13:20 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
A wafer-scale VLSI realization using optical reconfiguration architecture Atsushi Takata, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)  VLD2023-70 ICD2023-78 DC2023-77 RECONF2023-73 |
[more] | VLD2023-70 ICD2023-78 DC2023-77 RECONF2023-73 pp.205-208 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-17 13:45 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Parallel configuration experiment for a radiation-hardened optically reconfigurable gate array with a holographic polymer-dispersed liquid crystal memory Sae Goto, Minoru Watanabe (Okayama Univ.), Akifumi Ogiwara (Kobe City College of Technology), Nobuya Watanabe (Okayama Univ.) VLD2023-71 ICD2023-79 DC2023-78 RECONF2023-74 |
[more] | VLD2023-71 ICD2023-79 DC2023-78 RECONF2023-74 pp.209-214 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-17 15:15 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Maximum operating clock frequency evaluation of Mono Instruction Set Computers on an optically reconfigurable gate array VLSI Soma Imai, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) VLD2023-74 ICD2023-82 DC2023-81 RECONF2023-77 |
[more] | VLD2023-74 ICD2023-82 DC2023-81 RECONF2023-77 pp.227-230 |
| RECONF | 2023-09-14 15:00 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Monitoring system for optically reconfigurable gate arrays under radiation environments Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) RECONF2023-19 |
[more] | RECONF2023-19 pp.1-5 |
| RECONF | 2023-09-14 15:25 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Implementation of a sequential circuit onto an optically reconfigurable gate array VLSI without any crystal oscillator Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) RECONF2023-20 |
[more] | RECONF2023-20 pp.6-10 |
| RECONF | 2023-06-09 10:40 |
Kochi | Eikokuji Campus, Kochi University of Technology (Primary: On-site, Secondary: Online) |
Evaluation of low-voltage operations of an optically reconfigurable gate array VLSI Yuki Shimamura, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) RECONF2023-8 |
[more] | RECONF2023-8 pp.41-45 |
| RECONF | 2022-06-07 15:15 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Optically reconfigurable gate array VLSI with a perfect parallel configuration function Sae Goto, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) RECONF2022-6 |
[more] | RECONF2022-6 pp.32-36 |
| RECONF | 2022-06-07 15:40 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
290 Mrad total-ionizing-dose tolerance experiment for an optically reconfigurable gate array VLSI Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) RECONF2022-7 |
[more] | RECONF2022-7 pp.37-40 |
| RECONF | 2021-09-10 10:20 |
Online | Online | Convolutional neural network implementations using Vitis AI Akihiko Ushiroyama, Nobuya Watanabe, Akira Nagoya, Minoru Watanabe (Okayama Univ.) RECONF2021-19 |
Recently, Xilinx provides an FPGA-based Vitis AI development environment which is one of deep learning frameworks to acc... [more] | RECONF2021-19 pp.13-18 |
| RECONF | 2015-09-18 13:25 |
Ehime | Ehime University | Design of Hardware Description Language FSL Based on Object-Oriented/Functional Programming Languages Nobuya Watanabe, Akira Nagoya (Okayama Univ.) RECONF2015-37 |
This paper presents a new hardware description language FSL. The FSL inherits the design philosophy and the language fea... [more] | RECONF2015-37 pp.27-32 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-06 14:15 |
Kagoshima | Advice : An application design environment for various parallel processing hardware Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) CPSY2014-165 DC2014-91 |
We propose an application design environment: Advice (application design environment for various parallel processing har... [more] | CPSY2014-165 DC2014-91 pp.19-24 |
|
| RECONF | 2011-09-27 11:25 |
Aichi | Nagoya Univ. | A proposal of pattern matching techniques using dynamically reconfigurable hardware Masato Nogami, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) RECONF2011-37 |
The pattern matching of the strings using hardware has the problem that increases circuit size when the number of patter... [more] | RECONF2011-37 pp.87-92 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 10:55 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Feasibility of JHDL for Dynamically Reconfigurable Hardware Design Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) VLD2010-103 CPSY2010-58 RECONF2010-72 |
To develop applications for dynamically reconfigurable hardware, the description language which increases the efficienc... [more] | VLD2010-103 CPSY2010-58 RECONF2010-72 pp.133-138 |
| RECONF | 2009-09-18 09:50 |
Tochigi | Utsunomiya Univ. | Comparison and Evaluation of Application Implementation Methods for Dynamically Reconfigurable Processor DAPDNA-2 Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2009-30 |
Design tools are essential to implement applications on dynamically reconfigurable hardware efficiently, therefore to un... [more] | RECONF2009-30 pp.67-72 |
| RECONF | 2008-09-25 13:30 |
Okayama | Okayama Univ. | Implementation of JPEG Encoder on Dynamically Reconfigurable Processor and its Evaluation Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2008-24 |
Recently, dynamically reconfigurable hardware has been attracted, the research becomes active, and quantitative evaluati... [more] | RECONF2008-24 pp.7-12 |
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