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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2024-02-21 11:25 |
Tokyo | Tokyo University-Hongo-Engineering Bldg.4 (Primary: On-site, Secondary: Online) |
[Invited Talk]
Development of Backside Buried Metal Layer Technology to Enhance Power Integrity of Three-Dimensional Integrated Circuits Naoya Watanabe, Yuuki Araga, Haruo Shimamoto (AIST), Makoto Nagata (Kobe Univ.), Katsuya Kikuchi (AIST)  SDM2023-83 |
[more] | SDM2023-83 pp.9-15 |
| MRIS, ITE-MMS | 2020-10-05 15:25 |
Online | Online | [Invited Talk]
Fabrication of the fully-epitaxial magnetoresistance device on the poly-crystalline electrode using three-dimensional integration technology
-- Progress of fully-epitaxial magnetoresistance devices -- Yuya Sakuraba, Jiamin Chen (NIMS), Kay Yakushiji, Yuichi Kurashima, Naoya Watanabe, Akio Fukushima, Hideki Takagi, Katsuya Kikuchi, Shinji Yuasa (AIST), Kazuhiro Hono (NIMS) |
[more] | |
| ICD, SDM, ITE-IST [detail] | 2020-08-06 13:50 |
Online | Online | Over-the-top Si Interposer Embedding Backside Buried Metal to Reduce Power Supply Impedance Takuji Miki, Makoto Nagata, Akihiro Tsukioka (Kobe Univ.), Noriyuki Miura (Osaka Univ.), Takaaki Okidono (ECSEC), Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi (AIST) SDM2020-5 ICD2020-5 |
A 2.5D structure with a Si interposer stacked on a CMOS chip is developed to reduce power supply impedance. A backside b... [more] | SDM2020-5 ICD2020-5 pp.19-24 |
| SDM | 2019-02-07 13:10 |
Tokyo | [Invited Talk]
Stress Investigation of Annular-Trench-Isolated (ATI) Through Silicon Via (TSV) Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi (AIST) SDM2018-93 |
The methods as parylene substitute of SiO2 as dielectric layer and annular structure lose efficacy for thermal stress re... [more] | SDM2018-93 pp.9-14 |
|
| SDM | 2017-02-06 15:35 |
Tokyo | Tokyo Univ. | [Invited Talk]
Development of a Wet Cleaning Process for High-Yield Formation of via-last TSVs Naoya Watanabe (AIST), Hidekazu Kikuchi, Azusa Yanagisawa (LAPIS), Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi (AIST), Akio Nakamura (LAPIS) SDM2016-145 |
[more] | SDM2016-145 pp.35-40 |
| SDM | 2014-02-28 15:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
15μm-pitch Bump Interconnections Relied on Flip-chip Bonding Technique
-- for Advanced Chip Stacking Applications -- Masahiro Aoyagi, Thanh-Tung Bui, Fumiki Kato, Naoya Watanabe, Shunsuke Nemoto, Katsuya Kikuchi (AIST) SDM2013-173 |
This paper reports the development of reliable fine-pitch micro-bump Cu/Au interconnections relied on a high-precision r... [more] | SDM2013-173 pp.43-46 |
| ICD, SDM | 2012-08-02 11:00 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | Power Consumption Evaluation of COOL Chip : Heterogeneous Multi-Core Processors for energy-saving Embedded Systems Michiya Hagimoto, Hiroyuki Uchida, Takashi Omori, Yasumori Hibi, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Naoya Watanabe, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) |
[more] | |
| ICD, SDM | 2012-08-02 14:15 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | 3D Interconnect Technology by the Ultrawide-Interchip-Bus System for 3D Stacked LSI Systems Fumito Imura, Shunsuke Nemoto, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Hiroshi Nakagawa (AIST), Michiya Hagimoto, Hiroyuki Uchida, Takashi Omori, Yasumori Hibi, Yukoh Matsumoto (TOPS Systems), Masahiro Aoyagi (AIST) SDM2012-71 ICD2012-39 |
We have proposed the ultrawide-interchip-bus system for the interchip communication of the 3-dimentional stacked LSI sys... [more] | SDM2012-71 ICD2012-39 pp.43-48 |
| VLD | 2012-03-06 11:00 |
Oita | B-con Plaza | LSI Implementation of Heterogeneous Multi-Chip Processor for energy-saving Embedded Systems : COOL Chip Hiroyuki Uchida, Michiya Hagimoto, Tomoyuki Morimoto, Nobuyuki Hikichi, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Naoya Watanabe, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) VLD2011-122 |
The authors have suggested the low-power embedded heterogeneous multi-chip processor system: COOL Chip. We designed two ... [more] | VLD2011-122 pp.13-17 |
| SDM | 2011-02-07 11:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Application of Compliant Bump Technology to Image Sensor Naoya Watanabe, Tanemasa Asano (Kyushu Univ.) SDM2010-218 |
[more] | SDM2010-218 pp.13-18 |
| SDM, ED | 2009-06-24 17:00 |
Overseas | Haeundae Grand Hotel, Busan, Korea | Simulation and Experiment of Liquid-Phase Microjoining Using Cone-Shaped Compliant Bump Lijing Qiu (Kyushu Univ.), Naoya Watanabe (Fukuoka-IST), Tanemasa Asano (Kyushu Univ.) ED2009-66 SDM2009-61 |
In order to meet the requirements of high-density interconnection in 3D-LSI, we have proposed easy-deforming compliant b... [more] | ED2009-66 SDM2009-61 pp.71-74 |
| SDM | 2008-03-14 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Compliant Micro-Bumps for 3D Stacked-Chip LSIs with High Density Interconnection Implemented at Low Temperature Naoya Watanabe (Kumamoto TIF), Yutaka Iwasaki, Tanemasa Asano (Kyushu Univ.) SDM2007-276 |
We have proposed the compliant bump. The compliant bump, which can be made in the shape of pyramid or cone, has the pote... [more] | SDM2007-276 pp.17-20 |
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