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Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS 2019-04-12
13:30		 Miyagi Tohoku University An Improved RNS Binary Extended Euclidean Algorithm and a Residue Decoding Algorithm
Shinichi Kawamura (ECSEC TRA/Toshiba/AIST), Yuichi Komano, Hideo Shimizu (Toshiba) HWS2019-1		  [more] HWS2019-1
pp.1-6
ISEC 2009-05-22
11:10		 Tokyo Kikai-Shinko-Kaikan Bldg. Generalized Zero-offset Power Analyses for Restricted Masking Scheme
Yuichi Komano, Hideo Shimizu, Hanae Nozaki, Atsushi Shimbo (Toshiba Corp.) ISEC2009-4		  [more] ISEC2009-4
pp.21-28
IT, ISEC, WBS 2007-03-15
11:35		 Gunma Gunma Univ. (Kiryu Campus) Fault Attack on RSA using INSTAC-32 compliant platform
Koichi Fujisaki, Hideo Shimizu (TOSHIBA) 		 [more] IT2006-71 ISEC2006-126 WBS2006-68
pp.65-69
ISEC, IPSJ-CSEC, SITE 2005-07-21
11:35		 Iwate Iwate Prefectural University Development of DPA evaluation platform for 32 bit processor
Koichi Fujisaki, Hideo Shimizu, Atsushi Shimbo (Toshiba Corp.) 		 [more] ISEC2005-19 SITE2005-17
pp.75-82
ISEC 2004-09-17
13:50		 Tokyo Kikai-Shinko-Kaikan Bldg. A countermeasure against side channel attack using mask logic elements
Hideo Shimizu (Toshiba) 		We propose the new method of realizing the mask method which is a countermeasure against side channel attack of differen... [more] ISEC2004-69
pp.15-20
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