IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
NS 2023-04-14
11:40
Fukushima Nihon University, Koriyama Campus + Online
(Primary: On-site, Secondary: Online)
Network Anomaly Detection through Variable Granularity Traffic Analysis
Shohei Kamamura, Yuya Takeda (Seikei Univ.), Yuki Takei, Masato Nishiguchi, Yuhei Hayashi, Takayuki Fujiwara (NTT) NS2023-9
In the Society 5.0, it is important to accurately measure and analyze the communication traffic flow in wide-area IP net... [more] NS2023-9
pp.44-49
NS, IN
(Joint)
2022-03-10
09:10
Online Online Route Optimization for Traffic Engineering with Flow Re-routing Suppression
Masato Nishiguchi, Takayuki Fujiwara, Satoshi Nakatsukasa, Yuki Takei (NTT) NS2021-122
Traffic Engineering (TE) is an approach to optimize the utilization of network resources for reducing congestion in the ... [more] NS2021-122
pp.1-6
NS 2019-04-18
14:50
Kagoshima Tenmonkan Vision Hall [Invited Talk] The Trend of P4 Technology which Enable Programming of ASIC
Yuki Takei, Masato Nishiguchi, Masayuki Nishiki, Tomonori Takeda, Takayuki Fujiwara, Takamichi Kikkawa (NTT) NS2019-8
P4 is a programming language developed for the purpose of programming packet processing of network devices. It enables e... [more] NS2019-8
pp.43-48
NS, IN
(Joint)
2018-03-01
11:30
Miyazaki Phoenix Seagaia Resort A study of feasibility evaluation for performance estimation on network hardware abstraction
Yuki Takei, Satoshi Nishiyama, Saki Hatta, Koji Yamazaki (NTT) NS2017-186
When deploying the network functions at optimal positions by using the hardware devices such as CPU, FPGA and NPU, it is... [more] NS2017-186
pp.109-112
OPE, LQE 2016-06-17
11:25
Tokyo   1550nm range quantum dots laser integrated with composition-intermixed quantum dots waveguide
Shin'e Matsui, Yuki Takei (Waseda Univ.), Atsushi Matsumoto, Koichi Akahane (NICT), Yuichi Matsushima, Hiroshi Ishikawa, Katsuyuki Utaka (Waseda Univ.) OPE2016-11 LQE2016-21
We had developed composition-intermixing technique using ion implantation and rapid thermal annealing (QDI: Quantum Dots... [more] OPE2016-11 LQE2016-21
pp.11-14
LQE, OPE 2015-06-19
13:00
Tokyo   1550nm-Band Highly-Stacked QD Intermixing with Ar Implantation for Photonic Integrated Devices
Atsushi Matsumoto (NICT), Yuki Takei (Waseda Univ.), Kouichi Akahane, Naokatsu Yamamoto, Tetsuya Kawanishi (NICT), Hiroshi Ishikawa, Yuichi Matsushima, Katsuyuki Utaka (Waseda Univ.) OPE2015-12 LQE2015-22
In order to realize the monolithic optical integrated devices with using highly stacked semiconductor quantum dots struc... [more] OPE2015-12 LQE2015-22
pp.9-13
OCS, OPE, LQE 2014-10-30
13:15
Nagasaki Nagasaki Museum of History and Culture Gain Characteristics and Piezoelectric effect of 1550nm-Band QD-SOA Grown on InP(311)B Substrate for Ultra-Fast All-Optical Logic Gate Devices
Atsushi Matsumoto (NICT), Yuki Takei (Waseda Univ.), Kouichi Akahane (NICT), Hiroshi Ishikawa, Yuichi Matsushima, Katsuyuki Utaka (Waseda Univ.) OCS2014-58 OPE2014-102 LQE2014-76
In this paper, we fabricated the QD-SOA consisting of the 20-layer-stacked QDs structure with the strain-compensation te... [more] OCS2014-58 OPE2014-102 LQE2014-76
pp.87-91
OPE, LQE 2014-06-20
16:15
Tokyo   Study of Integration using Highly-Stacked Quantum Dots SOA and Intermixed Waveguide for All-Optical Logic Gate Devices
Yuki Takei, Atsushi Matsumoto, Asuka Matsushita (Waseda Univ.), Kouichi Akahane (NICT), Yuichi Matsushima, Hiroshi Ishikawa, Katsuyuki Utaka (Waseda Univ.) OPE2014-20 LQE2014-25
In this paper, we fabricated the QD-SOA and QDI-MMRs for the purpose of all optical logic gate device, and measured the ... [more] OPE2014-20 LQE2014-25
pp.35-38
LQE 2013-12-13
14:25
Tokyo   Fundamental Characteristics of 1550nm-Band 20-Layer-Stacked QD-SOA Grown on InP(311)B Substrate for All-Optical Logic Gate Device
Atsushi Matsumoto, Asuka Matsushita, Yuki Takei (Waseda Univ.), Kouichi Akahane (NICT), Yuichi Matsushima, Katsuyuki Utaka (Waseda Univ.) LQE2013-133
In this paper, we fabricated the QD-SOA which utilized the 20-layer-stacked quantum dots structure with the strain-compe... [more] LQE2013-133
pp.41-44
 Results 1 - 9 of 9  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan