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 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD 2011-08-26
13:40		 Toyama Toyama kenminkaikan Ultra low noise in-substrate-bitline sense amplifier for 4F2 DRAM array
Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Kazuo Ono, Riichiro Takemura (Hitachi) SDM2011-89 ICD2011-57		 An in-substrate-bitline sense amplifier (SA) with an array-noise-gating (ANG) scheme for stable sensing operation in a 4... [more] SDM2011-89 ICD2011-57
pp.93-97
SDM, ICD 2011-08-26
14:05		 Toyama Toyama kenminkaikan Sense Amplifier with Current Control Switch for Small-sized 0.5-V Gigabit-DRAM Arrays
Akira Kotabe, Yoshimitsu Yanagawa, Riichiro Takemura, Tomonori Sekiguchi, Kiyoo Itoh (Hitachi) SDM2011-90 ICD2011-58		  [more] SDM2011-90 ICD2011-58
pp.99-102
ICD 2011-04-19
14:00		 Hyogo Kobe University Takigawa Memorial Hall 1-Tbyte/s 1-Gbit Multicore DRAM Architecture using 3-D Integration for High-throughput Computing
Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Tomonori Sekiguchi (Hitachi, CRL) ICD2011-15		 A novel multicore DRAM architecture with an ultra high bandwidth and a large capacity is proposed for high throughput co... [more] ICD2011-15
pp.81-86
ICD, SDM 2010-08-26
13:00		 Hokkaido Sapporo Center for Gender Equality 1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing
Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Tomonori Sekiguchi (Hitachi) SDM2010-131 ICD2010-46		 A novel DRAM architecture with an ultra high bandwidth is proposed for high throughput computing. The proposed architect... [more] SDM2010-131 ICD2010-46
pp.39-44
ICD 2010-04-22
12:05		 Kanagawa Shonan Institute of Tech. Low-VT CMOS Preamplifier for 0.5-V Gigabit-DRAM Arrays
Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi (Hitachi) ICD2010-6		 A novel low-VT CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of the... [more] ICD2010-6
pp.29-33
SANE 2008-06-26
16:30		 Ibaraki Tsukuba Space Center (JAXA) Radiation-Induced Transient-Pulses in Logic LSIs for Use in Space Applications
Takahiro Makino (SOKENDAI), Yoshimitsu Yanagawa (U. Tokyo), Daisuke Kobayashi (SOKENDAI/JAXA), Seisuke Fukuda (JAXA), Kazuyuki Hirose, Hirokazu Ikeda (SOKENDAI/JAXA), Hirobumi Saito (U. Tokyo/JAXA), Shinobu Onoda, Toshio Hirao, Takeshi Ohshima (JAEA), Daisuke Takahashi, Shigeru Ishii, Masaki Kusano, Hiroshi Ikebuchi, Yoshikatsu Kuroda (MHI) SANE2008-25		 SET pulse-widths were measured as a function of LET by using pulse capture circuits.
In addition, a scan flip-flop (FF... [more]		 SANE2008-25
pp.67-72
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