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 Results 1 - 12 of 12  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-28
09:25		 Fukuoka Centennial Hall Kyushu University School of Medicine Routability-oriented Common-Centroid Capacitor Array Generation
Jing Li, Bo Yang (Design Algorithm Lab.), Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2012-89 DC2012-55		 We address layout generation of on-chip matched capacitors with the high relative accuracy. Unit capacitors are placed i... [more] VLD2012-89 DC2012-55
pp.171-175
IE, SIP, ICD, VLD, IPSJ-SLDM [detail] 2012-10-19
10:15		 Iwate Hotel Ruiz A 9-bit 10MSps SAR ADC with Double Input Range for Supply Voltage
Gong Chen, Yu Zhang, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang, Jing Li (Design Algorithm Lab.) VLD2012-49 SIP2012-71 ICD2012-66 IE2012-73		 This paper presents a pre-charge VCM-based method for 1.2V 9-bit 10MSps Successive Approximation
Register (SAR) ADC. Th... [more]		 VLD2012-49 SIP2012-71 ICD2012-66 IE2012-73
pp.49-53
IE, SIP, ICD, VLD, IPSJ-SLDM [detail] 2012-10-19
14:30		 Iwate Hotel Ruiz CMOS Op-amp Circuit Synthesis with Geometric Programming
Yu Zhang, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang, Jing Li (Design Algorithm Lab.) VLD2012-54 SIP2012-76 ICD2012-71 IE2012-78		 This work presents a 6T SRAM design in nanometer process via geometric programming (GP). We adopt the transistor array (... [more] VLD2012-54 SIP2012-76 ICD2012-71 IE2012-78
pp.77-82
KBSE 2011-11-10
12:40		 Nagano Shinshu Univ. Web Application Framework for End-User-Initiative Development with Domain Knowledge
Sei Ree, Takeshi Chusho (Meiji Univ) KBSE2011-39		 In recent years, many web applications are used in various business fields. These web applications are often developed o... [more] KBSE2011-39
pp.19-24
VLD 2011-09-26
14:00		 Fukushima University of Aizu A transistor-level symmetrical layout generation method for analog device
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2011-40		  [more] VLD2011-40
pp.1-4
VLD 2011-09-26
14:25		 Fukushima University of Aizu CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects
Yu Zhang, Gong Chen, Qing Dong, Jing Li, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2011-41		  [more] VLD2011-41
pp.5-10
VLD 2011-03-02
16:20		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Reusable Constraints of Nano-watt BGR Circuits in CMOS Process Migration
Gong Chen, Delong Yin, Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2010-123		  [more] VLD2010-123
pp.43-47
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-12-01
13:55		 Fukuoka Kyushu University Analysis of Channel Decomposition for Structured Analog Layout and Low-power Applications
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2010-79 DC2010-46		  [more] VLD2010-79 DC2010-46
pp.161-166
CAS, MSS, VLD, SIP 2010-06-21
11:40		 Hokkaido Kitami Institute of Technology Layout-Aware Variation Modeling and Its Application to Opamp Design
Kouta Shinohara, Mihoko Hidaka, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) CAS2010-7 VLD2010-17 SIP2010-28 CST2010-7		 As geometrical scaling of the transistor dimensions, such as feature
size and supply voltage, has dominated the semicon... [more]		 CAS2010-7 VLD2010-17 SIP2010-28 CST2010-7
pp.37-41
VLD 2010-03-10
13:55		 Okinawa   Analog Macro Layout Generation Based on Regular Bulk Structure
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2009-100		  [more] VLD2009-100
pp.7-12
VLD, CAS, SIP 2008-06-27
10:35		 Hokkaido Hokkaido Univ. A Large-scale Placement Framework Based on Mathematical Programming
Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) CAS2008-23 VLD2008-36 SIP2008-57		  [more] CAS2008-23 VLD2008-36 SIP2008-57
pp.25-29
VLD, ICD 2008-03-05
15:20		 Okinawa TiRuRu Analog Floorplan with Soft-Module Configuration
Kentarou Murata, Kazuya Sasaki, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2007-142 ICD2007-165		 In MOS analog design,
the transistor size is increasing as the supply voltage becomes lower, and the layout configurat... [more]		 VLD2007-142 ICD2007-165
pp.31-36
 Results 1 - 12 of 12  /   
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