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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2012-03-07
13:20		 Oita B-con Plaza Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor
Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-138		 This paper describes a DVFS technique to reduce energy dissipation of Dynamically Reconfigurable Processors(DRP). DRP’s ... [more] VLD2011-138
pp.109-114
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
14:10		 Kanagawa Keio Univ (Hiyoshi Campus) Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead
Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute) VLD2010-92 CPSY2010-47 RECONF2010-61		 This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Proces... [more] VLD2010-92 CPSY2010-47 RECONF2010-61
pp.49-54
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