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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RCS, NS
(Joint)		 2018-12-21
09:50		 Hiroshima Onomichi City Hall Transmission performance for computer simulation and experiment in LoRaWAN CSS modulation scheme and its application of positioning service
Kyouka Abe (Grad. Sch. Suwa University of Science), Taisei Muramatsu, Keigo Nakajima, Miune Taguchi, Kazuhiro Yamaguchi, Hideaki Matsue (Suwa University of Science), Atsushi Iguchi (IDEA SYSTEM), Tasuku Hiroshima (Oi Electric) RCS2018-233		 Computer simulation and field experiment for LoRaWAN CSS modulation scheme are carried out. As a results, BER performa... [more] RCS2018-233
pp.83-87
SDM, ICD 2011-08-25
09:00		 Toyama Toyama kenminkaikan Study of pattern area reduction with 3 dimensional transistor for logic circuit
Takahiro Kodama, Shigeyoshi Watanabe (SIT), Yu Hiroshima (Oi Electric) SDM2011-71 ICD2011-39		  [more] SDM2011-71 ICD2011-39
pp.1-6
ICD 2009-12-14
13:30		 Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] Reducing pattern area technology of 3D transistor for system LSI
Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-78		 We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] ICD2009-78
pp.13-18
VLD 2009-03-13
15:15		 Okinawa   Reduced pattern area technology of 3D transistor for system LSI
Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2008-167		 We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] VLD2008-167
pp.243-248
ICD, SDM 2008-07-17
15:30		 Tokyo Kikai-Shinko-Kaikan Bldg. New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI
Yu Hiroshima, Shigeyoshi Watanabe (SIT) SDM2008-137 ICD2008-47		  [more] SDM2008-137 ICD2008-47
pp.53-58
SDM 2008-03-14
16:15		 Tokyo Kikai-Shinko-Kaikan Bldg. New design technology of independent-gate controlled Double-Gate transistor for LSI
Yu Hiroshima, Keisuke Okamoto, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2007-279		  [more] SDM2007-279
pp.33-38
VLD, ICD 2008-03-07
16:10		 Okinawa TiRuRu New technology of independent-gate controlled Double-Gate transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-168 ICD2007-191		 New design technology of independent-gate controlled Double-Gate transistor realized high density design more than FinFE... [more] VLD2007-168 ICD2007-191
pp.69-74
VLD, ICD 2008-03-07
16:35		 Okinawa TiRuRu New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-169 ICD2007-192		 New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controll... [more] VLD2007-169 ICD2007-192
pp.75-80
VLD, ICD 2008-03-07
17:00		 Okinawa TiRuRu Design of High Density LSI with Three-Dimensional Transistor FinFET -- Effect of pattern Area Reduction with CMOS Cell Library --
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-170 ICD2007-193		 (To be available after the conference date) [more] VLD2007-170 ICD2007-193
pp.81-86
ICD, SDM 2007-08-24
13:50		 Hokkaido Kitami Institute of Technology Design of High Density LSI with Three-Dimensional Transistor FinFET -- Effect of Pattern Area Reduction with CMOS Cell Library --
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (SIT) SDM2007-163 ICD2007-91		 New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of CMO... [more] SDM2007-163 ICD2007-91
pp.119-124
ICD, SDM 2007-08-24
14:15		 Hokkaido Kitami Institute of Technology Ｄesign Method of system LSI with FinFET type DTMOS
Yu Hiroshima, Shigeyoshi Watanabe, Keisuke Okamoto, Keisuke Koizumi (SIT) SDM2007-164 ICD2007-92		 Planar DTMOS has a problem of increase of pattern area. Using FinFET type DTMOS excess pattern area of connect to gate a... [more] SDM2007-164 ICD2007-92
pp.125-130
 Results 1 - 11 of 11  /   
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