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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2018-12-06
13:00		 Hiroshima Satellite Campus Hiroshima Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-56 DC2018-42		 3D die-stacking technique using TSVs has gained much attention as a new integration method of IC.
However, faulty TSVs ... [more]		 VLD2018-56 DC2018-42
pp.119-124
DC 2018-02-20
10:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2017-79		 TSV attracts attention as a new implementation method of interconnects between dies in 3DICs.
However, faulty TSVs may ... [more]		 DC2017-79
pp.13-18
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