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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY | 2011-10-21 15:50 |
Hyogo | A Feasibility Study of Home Services Using a Microphone Array Network Shimpei Soda, Shinsuke Matsumoto, Masahide Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)  CPSY2011-36 |
The home network system (HNS), which provides value-added services by orchestrating networked home appliances, equipment... [more] | CPSY2011-36 pp.61-66 |
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| ICD | 2011-04-19 09:30 |
Hyogo | Kobe University Takigawa Memorial Hall | 0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM Koji Yanagida, Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Hiroshi Kawaguchi (Kobe Univ.) ICD2011-8 |
We proposes a dependable dual-port SRAM with 9T/18T bitcell structure. The proposed SRAM has two operating modes: a 9T n... [more] | ICD2011-8 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 09:50 |
Fukuoka | Kyushu University | Fault-Injection using Virtualized Environment for Validating Automotive Systems Yasuhiro Ito (Hitachi.), Yohei Nakata, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Yasuo Sugure, Shigeru Oho (Hitachi.) VLD2010-73 DC2010-40 |
Fault Injection System: a system level co-simulation environment with fault-injection in memory access was developed. It... [more] | VLD2010-73 DC2010-40 pp.119-123 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 10:10 |
Fukuoka | Kyushu University | Evaluation and Verification of Dependable Processor Architecture Using System-Level Fault-Injection Scheme Yohei Nakata (Kobe Univ.), Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (Hitachi Ltd.), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) VLD2010-74 DC2010-41 |
We develop a fault case generator that can generate memory failures in aprocessor-in-the-loop simulation. The fault inje... [more] | VLD2010-74 DC2010-41 pp.125-130 |
| IPSJ-SLDM, SIP, IE, ICD [detail] | 2010-10-05 14:00 |
Chiba | Makuhari Messe, International Conference Hall | 7T SRAM Enabling Low-Energy Simultaneous Block Copy Shunsuke Okumura, Yuki Kagiyama, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SIP2010-57 ICD2010-71 IE2010-75 |
This paper proposes 7T SRAM which realizes block level simultaneous copying feature. The proposed SRAM can be used for d... [more] | SIP2010-57 ICD2010-71 IE2010-75 pp.49-54 |
| IPSJ-SLDM, SIP, IE, ICD [detail] | 2010-10-06 11:50 |
Chiba | Makuhari Messe, International Conference Hall | Data-Intensive Sound Acquisition with Data Aggregation Protocol for Microphone Array Networks Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shimpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.) SIP2010-67 ICD2010-81 IE2010-85 |
We propose a microphone array network that realizes ubiquitous sound acquisition. A number of nodes with sixteen microph... [more] | SIP2010-67 ICD2010-81 IE2010-85 pp.95-100 |
| ICD, ITE-IST | 2009-10-02 16:10 |
Tokyo | CIC Tokyo (Tamachi) | A 58-uW Single-Chip Sensor Node Processor Using Synchronous MAC Protocol Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto (Kobe Univ.) ICD2009-58 |
In this paper, we propose a single-chip ultra low-power sensor node processor with a synchronous media access control (M... [more] | ICD2009-58 pp.141-145 |
| ICD | 2009-04-14 10:40 |
Miyagi | Daikanso (Matsushima, Miyagi) | A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2009-6 |
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster a... [more] | ICD2009-6 pp.27-32 |
| ICD | 2009-04-14 11:05 |
Miyagi | Daikanso (Matsushima, Miyagi) | A 7T/14T Dependable SRAM and Its Array Structure to Avoid Half Selection Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST-CREST) ICD2009-7 |
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. The dep... [more] | ICD2009-7 pp.33-38 |
| IN, NS (Joint) |
2009-03-03 11:30 |
Okinawa | Okinawa-Zanpamisaki Royal Hotel | Isochronous MAC Protocol for Low-Power Wireless Sensor Node VLSI Shintaro Izumi, Takashi Matsuda, Takashi Takeuchi, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto (Kobe Univ.) NS2008-174 |
In this paper, we propose the isochronous media access control (I-MAC) processor by cross layer design. The I-MAC can be... [more] | NS2008-174 pp.177-182 |
| ICD | 2008-12-12 16:10 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control Kosuke Yamaguchi, Hidehiro Fujiwara, Takashi Takeuchi, Yu Otake, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kove Univ) ICD2008-127 |
We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-... [more] | ICD2008-127 pp.131-136 |
| ICD, ITE-IST | 2008-10-24 10:25 |
Hokkaido | Hokkaido University | Variable bandwidth digital bandpass filter for cognitive radio Koh Tsuruda, Shintaro Izumi, Hyeokjong Lee, Takashi Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2008-82 |
In this paper, we propose a reconfigurable baseband processor for a cognitive radio that has multi-resolution bandpass f... [more] | ICD2008-82 pp.137-142 |
| VLD, IPSJ-SLDM | 2008-05-09 13:55 |
Hyogo | Kobe Univ. | A Sub 100 mW H.264/AVC MP@L4.1 Integer-Pel Motion Estimation Processor VLSI for MBAFF Encoding Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
[more] | VLD2008-11 pp.25-30 |
| VLD, IPSJ-SLDM | 2008-05-09 14:35 |
Hyogo | Kobe Univ. | A Dependable SRAM with high-reliability mode and high-speed mode. Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, “quality of a bit （QoB）” for i... [more] | VLD2008-12 pp.31-36 |
| ICD, ITE-CE | 2007-12-13 17:15 |
Kochi | A Power-Efficient SRAM Core Architecture with Segmentation-Free and Rectangular Accessibility for Super-Parallel Video Processing Yuichiro Murachi, Junichi Miyakoshi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-128 |
This paper describes a unique SRAM architecture for super-parallel video processing. It features one cycle functional ac... [more] | ICD2007-128 pp.47-52 |
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| ICD, ITE-CE | 2007-12-14 10:20 |
Kochi | A VGA 30-fps Real-Time Optical-Flow Processor Core for Moving Picture Recognition Hajime Ishihara, Masayuki Miyama (Kanazawa Univ.), Yuichiro Murachi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.), Yoshio Matsuda (Kanazawa Univ.) ICD2007-131 |
This paper proposes an optical-flow processor for real-time video recognition. This processor is based on the Pyramidal ... [more] | ICD2007-131 pp.65-70 |
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| ICD, SDM | 2007-08-24 15:40 |
Hokkaido | Kitami Institute of Technology | An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2007-167 ICD2007-95 |
This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM... [more] | SDM2007-167 ICD2007-95 pp.139-144 |
| ICD, ITE-IST | 2007-07-26 15:40 |
Hyogo | Cross-Layer Design for Low-Power Wireless Sensor Node using Long-Wave Standard Time Code Yu Otake, Masumi Ichien, Takashi Takeuchi, Akihiro Gion, Shinji Mikami, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto (Kobe Univ.) ICD2007-49 |
We propose Isochronous-MAC (I-MAC) using the Long-Wave Standard Time Code, and introduce cross-layer design for a low-po... [more] | ICD2007-49 pp.71-76 |
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| ICD, ITE-IST | 2007-07-26 16:05 |
Hyogo | A 356-µW, 433-MHz, Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks Hyeokjong Lee, Shinji Mikami, Takashi Takeuchi, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto (Kobe Univ.) ICD2007-50 |
We describe a low-power voltage amplifier that is suitable for RF (radio frequency) receivers in a WSN (wireless sensor ... [more] | ICD2007-50 pp.77-82 |
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| ICD, ITE-IST | 2007-07-26 17:05 |
Hyogo | Low power consumption of H.264/AVC decoder with dynamic voltage and frequency scaling Yoshinori Sakata, Kentaro Kawakami, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-52 |
We propose an elastic pipeline architecture that can apply dynamic voltage scaling (DVS) to a dedicated hardware, and ap... [more] | ICD2007-52 pp.89-94 |
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