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All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 8件中 1~8件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2015-06-19
10:50
Aichi VBL, Nagoya Univ. [Invited Lecture] Investigation of SiC MOSFETs with 3C/4H Different Poly-Type Junctions
Muentaka Noguchi, Toshiaki Iwamatsu, Naruhisa Miura, Shuhei Nakata, Satoshi Yamakawa (Mitsubishi Electric)
SiliconCarbide (SiC) have different poly-types, which shows various energy bandgap. This suggests the possibility of SiC... [more] SDM2015-41
pp.17-20
SDM 2014-01-29
14:40
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation
Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii (LEAP), Koichiro Ishibashi (Univ. of Electro- Comm.), Tomoko Mizutani, Toshiro Hiramoto (Univ. of Tokyo), Yasuo Yamaguchi (LEAP)
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] SDM2013-143
pp.35-38
SDM, ICD 2013-08-02
09:25
Ishikawa Kanazawa University Reduced Cell Current Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells at Supply Voltage of 0.4V
Tomoko Mizutani (Univ. of Tokyo), Yoshiki Yamamoto, Hideki Makiyama, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii (LEAP), Toshiro Hiramoto (Univ. of Tokyo)
Cell current (ICELL) variability in 6T-SRAM composed of silicon-on-thin-BOX (SOTB) MOSFETs by 65nm technology is measure... [more] SDM2013-75 ICD2013-57
pp.47-52
ICD, SDM 2012-08-02
13:00
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido [Invited Lecture] Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power (ULP) Applications
Nobuyuki Sugii, Toshiaki Iwamatsu, Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Hirofumi Shinohara, Hideki Aono, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (LEAP/Renesas), Tomoko Mizutani, Toshiro Hiramoto (IIS, The University of Tokyo)
Needs for low-power CMOS devices are still increasing. Ultralow-voltage-operation (ULV) CMOS with maximum power efficien... [more] SDM2012-68 ICD2012-36
pp.29-32
ICD, SDM 2012-08-02
13:25
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido Reduced Drain Current Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) MOSFETs
Tomoko Mizutani (Univ. of Tokyo), Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii (LEAP), Toshiro Hiramoto (Univ. of Tokyo)
Drain current variability in silicon-on-thin-BOX (SOTB) MOSFETs by 65nm technology is analyzed and compared with convent... [more] SDM2012-69 ICD2012-37
pp.33-36
SDM, ED
(Workshop)
2012-06-29
09:45
Okinawa Okinawa Seinen-kaikan [Invited Talk] Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power (ULP) Applications
Nobuyuki Sugii, Toshiaki Iwamatsu, Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Hirofumi Shinohara, Hideki Aono, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (LEAP/Renesas), Tomoko Mizutani, Toshiro Hiramoto (IIS, Univ. of Tokyo)
Needs for low-power CMOS devices are still increasing. Ultralow-voltage-operation CMOS with maximum power efficiency can... [more]
ICD 2010-04-22
09:50
Kanagawa Shonan Institute of Tech. [Invited Talk] Challenging for an ultra low-voltage SRAM by innovative design circuits and device technologies -- A 0.5V 100MHz PD-SOI SRAM using Asymmetric MOSFET and Forward Body Bias --
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara (Renesas Electronics)
We investigate 0.5V 6T-SRAM with asymmetric MOSFET, which contributes to enhance the read and write margin. We also intr... [more] ICD2010-2
pp.7-12
ICD, SDM 2008-07-17
15:05
Tokyo Kikai-Shinko-Kaikan Bldg. A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention
Norifumi Kameshiro, Takao Watanabe, Tomoyuki Ishii, Toshiyuki Mine (Hitachi, Ltd.), Toshiaki Sano (Renesas), Hidefumi Ibe, Satoru Akiyama (Hitachi, Ltd.), Kazumasa Yanagisawa, Takashi Ipposhi, Toshiaki Iwamatsu, Yasuhiko Takahashi (Renesas)
We proposed a fully logic compatible process for a single electron shut-off transistor (SESO). A 1-kb memory-cell array ... [more] SDM2008-136 ICD2008-46
pp.47-52
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