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Committee Date Time Place Paper Title / Authors Abstract Paper #
IN, NV
(Joint)		 2013-07-18
15:40		 Hokkaido Hokkaido Univ. Faculty of Eng. Academic Lounge 3 [Invited Talk] Fast Algorithms for Counting the Number of Paths in a Grid Graph
Hiroaki Iwashita (JST) IN2013-44		 A path in a graph, which is also referred to as a self-avoiding walk (SAW), is a way to go from a vertex to another vert... [more] IN2013-44
pp.49-54
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-26
10:55		 Fukuoka Centennial Hall Kyushu University School of Medicine An Efficient ZDD Construction Method Using Recursive Specifications
Hiroaki Iwashita, Jun Kawahara (JST), Shin-ichi Minato (Hokkaido Univ.) VLD2012-63 DC2012-29		 In recent years, new enumeration methods using zero-suppressed binary decision diagrams (ZDDs) has been attracting atten... [more] VLD2012-63 DC2012-29
pp.25-29
VLD, IPSJ-SLDM 2007-05-11
09:30		 Kyoto Kyodai Kaikan Automatic Generation of a Verification Environment for Hardware Units -- Application to a Bus Bridge Design --
Rafael Kazumiti Morizawa, Hiroaki Iwashita, Koichiro Takayama (Fujitsu Labs.) VLD2007-7		 The verification cost of complex SoCs has been increasing in a fast pace. Many techniques and methodologies have been de... [more] VLD2007-7
pp.1-6
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2006-11-28
09:00		 Fukuoka Kitakyushu International Conference Center A methodology of generating verification scenarios from specification
Ryosuke Oishi, Akio Matsuda, Hiroaki Iwashita, Koichiro Takayama (Fujitsu Labs. LTD.) 		 [more] VLD2006-51 DC2006-38
pp.1-4
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