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Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2008-03-14 16:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | New design technology of independent-gate controlled Double-Gate transistor for LSI Yu Hiroshima, Keisuke Okamoto, Shigeyoshi Watanabe (Shonan Inst. of Tech.)  SDM2007-279 |
[more] | SDM2007-279 pp.33-38 |
| VLD, ICD | 2008-03-07 16:10 |
Okinawa | TiRuRu | New technology of independent-gate controlled Double-Gate transistor for system LSI Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-168 ICD2007-191 |
New design technology of independent-gate controlled Double-Gate transistor realized high density design more than FinFE... [more] | VLD2007-168 ICD2007-191 pp.69-74 |
| VLD, ICD | 2008-03-07 16:35 |
Okinawa | TiRuRu | New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-169 ICD2007-192 |
New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controll... [more] | VLD2007-169 ICD2007-192 pp.75-80 |
| VLD, ICD | 2008-03-07 17:00 |
Okinawa | TiRuRu | Design of High Density LSI with Three-Dimensional Transistor FinFET
-- Effect of pattern Area Reduction with CMOS Cell Library -- Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-170 ICD2007-193 |
(To be available after the conference date) [more] | VLD2007-170 ICD2007-193 pp.81-86 |
| ICD, SDM | 2007-08-24 13:50 |
Hokkaido | Kitami Institute of Technology | Design of High Density LSI with Three-Dimensional Transistor FinFET
-- Effect of Pattern Area Reduction with CMOS Cell Library -- Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (SIT) SDM2007-163 ICD2007-91 |
New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of CMO... [more] | SDM2007-163 ICD2007-91 pp.119-124 |
| ICD, SDM | 2007-08-24 14:15 |
Hokkaido | Kitami Institute of Technology | Ｄesign Method of system LSI with FinFET type DTMOS Yu Hiroshima, Shigeyoshi Watanabe, Keisuke Okamoto, Keisuke Koizumi (SIT) SDM2007-164 ICD2007-92 |
Planar DTMOS has a problem of increase of pattern area. Using FinFET type DTMOS excess pattern area of connect to gate a... [more] | SDM2007-164 ICD2007-92 pp.125-130 |
| SDM | 2007-03-15 14:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Impact of three-dimensional transistor on the pattern area reduction for high density ULSI Shigeyoshi Watanabe, Keisuke Okamoto, Yuu Hiroshima, Ｋｅｉｓｕｋｅ Ｋｏｉｚｕｍｉ, Makoto Oya (SIT) |
[more] | SDM2006-257 pp.15-20 |
| ICD, VLD | 2007-03-09 13:40 |
Okinawa | Mielparque Okinawa | Ｄesign Method of High Density System LSI with Three-Dimensional Transistor (FinFET)
-- Pattern Area Reduction of System LSI -- Shigeyoshi Watanabe, Keisuke Okamoto, Makoto Oya (Shonan Institute of Tech.) |
[more] | VLD2006-149 ICD2006-240 pp.51-56 |
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-27 10:30 |
Miyagi | Design Method of System LSI with Three-Dimensional Transistor (FinFET)
-- Reduction of pattern Area -- Shigeyoshi Watanabe, Keisuke Okamoto, Makoto Oya (SIT) |
New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of sys... [more] | SIP2006-105 ICD2006-131 IE2006-83 pp.25-30 |
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