IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2009-03-05
15:45
Niigata Sado Island Integrated Development Center Single-Cycle-Accessible Two-Level Cache Architecture
Seiichiro Yamaguchi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) CPSY2008-91 DC2008-82
A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the ener... [more] CPSY2008-91 DC2008-82
pp.19-24
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2008-03-27
08:45
Kagoshima   An Adaptive Multi-Performance Processor and its Evaluation
Seiichiro Yamaguchi, Yuichiro Oyama (Kyushu Univ.), Yuji Kunitake (Kyushu Inst. of Tech.), Tadayuki Matsumura, Yuriko Ishitobi, Masaki Yamaguchi, Donghoon Lee, Yusuke Kaneda (Kyushu Univ.), Toshimasa Funaki (Kyushu Inst. of Tech.), Masanori Muroyama, Tohru Ishihara, Toshinori Sato (Kyushu Univ.) DC2007-84 CPSY2007-80
This paper presents an energy efficient processor which can be used as a design alternative for the dynamic voltage scal... [more] DC2007-84 CPSY2007-80
pp.1-6
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-20
10:05
Fukuoka Kitakyushu International Conference Center A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
Memory systems consume a significant amount of the energy in embedded systems. Static code placement techniques using sc... [more] VLD2007-74 DC2007-29
pp.25-29
VLD, IPSJ-SLDM 2006-05-11
15:00
Ehime Ehime University A Software-level Energy Reduction Technique for Embedded Microprocessor Exploiting Narrow Bitwidth Operations
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
This paper proposes a software-level energy reduction technique for microprocessor-based embedded systems. A basic idea ... [more] VLD2006-3
pp.13-18
 Results 1 - 4 of 4  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan