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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 6件中 1~6件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CAS, MSS, IPSJ-AL [detail] 2019-11-28
11:15
Fukuoka   Ising model solver for combinatorial optimization problems with constraints
Fumiyo Takano, Motoi Suzuki, Yuki Kobayashi, Takuya Araki (NEC)
 [more]
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
09:25
Hiroshima Satellite Campus Hiroshima Transparent Acceleration Method for Network Function Virtualization Using FPGA
Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Baba Hiroshi (NEC)
Network Function Virtualization (NFV) is becoming a new networking architecture for telecom carriers.
While NFV reali... [more]
RECONF2018-38
pp.21-26
CAS, SIP, MSS, VLD 2018-06-15
16:25
Hokkaido Hokkaido Univ. (Frontier Research in Applied Sciences Build.) *
Tomotaka Inoue, Kento Hasegawa (Waseda Univ.), Yuki Kobayashi (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(To be available after the conference date) [more] CAS2018-33 VLD2018-36 SIP2018-53 MSS2018-33
pp.173-178
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
14:00
Kumamoto Kumamoto-Kenminkouryukan Parea *
Tomotaka Inoue, Kento Hasegawa (Waseda Univ.), Yuki Kobayashi (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
 [more] VLD2017-51 DC2017-57
pp.133-138
VLD 2017-03-02
13:30
Okinawa Okinawa Seinen Kaikan [Invited Talk] Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture
Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC)
CPU-FPGA tightly coupled architecture is an emerging architecture where FPGA is tightly coupled with CPU. We introduce a... [more] VLD2016-115
p.79
RECONF 2016-09-06
09:10
Toyama Univ. of Toyama [Invited Talk] Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture
Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC)
CPU-FPGA tightly coupled architecture is an emerging architecture where FPGA is tightly coupled with CPU. We introduce a... [more] RECONF2016-32
p.37
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