|
|
All Technical Committee Conferences (Searched in: All Years)
|
|
Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
|
Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF |
2016-05-19 16:35 |
Kanagawa |
FUJITSU LAB. |
Optically reconfigurable gate arrary with an optical input Hiroki Shinba, Shinya Furukawa (Shizuoka Univ.), Ili Shairah Abdul Halim (MJIIT), Minoru Watanabe (Shizuoka Univ.), Fuminori Kobayashi (MJIIT) RECONF2016-14 |
[more] |
RECONF2016-14 pp.67-70 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 14:40 |
Fukuoka |
Kitakyushu International Conference Center |
An approach to Place and Route challenges in Dynamic Reconfiguration Ryo Hidaka, Fuminori Kobayashi (Kyushu Inst. of Tech.), Minoru Watanabe (Shizuoka Univ.) RECONF2007-38 |
Recently, though the dynamically reconfigurable devices begin to be practical, these devices change the circuit with tim... [more] |
RECONF2007-38 pp.13-17 |
RECONF |
2006-09-14 13:00 |
Kumamoto |
Kumamoto Univ. |
Optically Reconfigurable Gate Array with manufacturing defect tolerance Ryo Hidaka, Minoru Watanabe, Fuminori Kobayashi (Kyutech) |
[more] |
RECONF2006-20 pp.1-5 |
RECONF |
2006-09-14 13:30 |
Kumamoto |
Kumamoto Univ. |
Reconfiguration speed and power consumption adjustment method for Optically Differential Reconfigurable Gate Arrays Ryo Hidaka, Minoru Watanabe, Fuminori Kobayashi (Kyutech) |
[more] |
RECONF2006-21 pp.7-11 |
RECONF |
2006-09-14 14:00 |
Kumamoto |
Kumamoto Univ. |
An Optically Reconfigurable Gate Array with a liquid crystal hologram Yoshiyuki Nakada, Minoru Watanabe, Fuminori Kobayashi (Kyutech) |
[more] |
RECONF2006-22 pp.13-16 |
CAS |
2006-01-13 10:50 |
Miyazaki |
|
Characteristics Improvement of PLLs Using Phase Interpolation
-- Circuit Optimization of Phase Interpolation -- Manabu Inoue, Fuminori Kobayashi, Minoru Watanabe (KIT) |
Normal PLL (Phase Locked Loop) compares phases of reference and input at the time of their positive transition. We propo... [more] |
CAS2005-89 pp.13-17 |
ICD |
2005-07-14 15:20 |
Aichi |
Toyohashi Univ. of Tech. |
An evalution of 272 gate count ODRGA_VLSI Takenori Shiki, Minoru Watanabe, Fuminori Kobayashi (K I T) |
[more] |
ICD2005-50 pp.61-65 |
ICD |
2005-07-14 15:45 |
Aichi |
Toyohashi Univ. of Tech. |
Reconfiguration Speed Improvement of an ODRGA using VCSELs Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi (KIT) |
[more] |
ICD2005-51 pp.67-70 |
IE, SIP, ICD, IPSJ-SLDM |
2004-10-21 15:00 |
Yamagata |
|
An Optically Differential Reconfigurable Gate Array using a 0.18 um CMOS process Minoru Watanabe, Fuminori Kobayashi (Kyushu Institute of Technology) |
[more] |
SIP2004-86 ICD2004-118 IE2004-62 pp.61-66 |
|
|
|
Copyright and reproduction :
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
|
[Return to Top Page]
[Return to IEICE Web Page]
|