IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CS, CAS 2020-02-27
14:05		 Kumamoto   [Invited Lecture] Implementation of a Software-based Time-aware Shaper for TSN
Yasin Oge, Yuta Kobayashi, Takahiro Yamaura, Tomonori Maegawa (Toshiba) CAS2019-106 CS2019-106		 In this lecture, we present the design, implementation, and evaluation of a time-aware shaper, which is a traffic shaper... [more] CAS2019-106 CS2019-106
pp.49-54
NS 2019-01-18
14:35		 Nagasaki Nagasaki Prefectural Art Museum [Encouragement Talk] Timing-Accuracy Evaluation of a Time-aware Shaper for IEEE 802.1Qbv using Time-based Transmission Scheme
Yasin Oge, Yuta Kobayashi, Takahiro Yamaura, Tomonori Maegawa (Toshiba) NS2018-186		 This paper presents an implementation and evaluation of a time-aware shaper, a traffic shaper specifically designed for ... [more] NS2018-186
pp.47-52
NS 2018-05-18
10:20		 Kanagawa Yokohama City Education Center Implementation and Evaluation of a Time-aware Shaper for IEEE 802.1Qbv using Time-based Transmission Scheme
Yasin Oge, Yuta Kobayashi, Takahiro Yamaura, Tomonori Maegawa (Toshiba) NS2018-25		 This paper presents an implementation and evaluation of a time-aware shaper, a traffic shaper specifically designed for ... [more] NS2018-25
pp.57-62
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2009-12-02
15:40		 Kochi Kochi City Culture-Plaza Two-level Cache Simulation with L2 Unified Cache for Embedded Applications
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-47 DC2009-34		 In this paper, we propose a two-level cache simulation method with L2 unified cache for embedded applications. It simula... [more] VLD2009-47 DC2009-34
pp.37-42
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
12:45		 Kanagawa   A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-116 CPSY2008-78 RECONF2008-80		 In this paper, we propose an energy-efficient ASIP synthesis method based on reducing instruction memory access. Since a... [more] VLD2008-116 CPSY2008-78 RECONF2008-80
pp.147-152
 Results 1 - 5 of 5  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan