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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 11:15 |
Kanagawa | Hiyoshi Campus, Keio University | A FPGA/GPU cooperation in nodes communication using PEACH2 Takuya Kuhara, Takaaki Miyajima (Keio Univ.), Toshihiro Hanawa (Tokyo Univ.), Hideharu Amano (Keio Univ.), Taisuke Boku (Univ. of Tsukuba)  VLD2013-108 CPSY2013-79 RECONF2013-62 |
PEACH2 (PCI-Express Adaptive Communication Hub 2) is a inter/intra node communication enhancement system for HA-PACS, w... [more] |
VLD2013-108 CPSY2013-79 RECONF2013-62 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 10:30 |
Kagoshima | A circuit division method for High-Level synthesis on Multi-FPGA systems in stream processing Daiki Kugami, Takaaki Miyajima, Hideharu Amano (Keio Univ.) CPSY2013-68 |
High-Level Synthesis (HLS) has been utilized as a practical tool especially for designing Field Programmable Gate Array... [more] |
CPSY2013-68 pp.53-58 |
|
| RECONF | 2013-09-19 13:25 |
Ishikawa | Japan Advanced Institute of Science and Technology | A study of pipeline execution on PEACH2 Takaaki Miyajima, Takuya Kuhara (Keio Univ.), Toshihiro Hanawa (Tsukuba Univ.), David Thomas (Imperial College), Hideharu Amano (Keio Univ.) RECONF2013-33 |
PEACH2 (PCI-Express Adaptive Communication Hub 2) is a inter/intra node communication enhance- ment system for HA-PACS, ... [more] | RECONF2013-33 pp.79-84 |
| RECONF | 2013-05-21 10:35 |
Kochi | Kochi Prefectural Culture Hall | Implementation of Speculative Gather System for CMA Rie Uno, Nobuaki Ozaki, Mai Izawa, Akihito Tsusaka, Takaaki Miyajima, Hideharu Amano (Keio Univ.) RECONF2013-11 |
Cool Mega Array (CMA) is a low power reconfigurable processor array for battery driven mobile devices. A prototype chip ... [more] | RECONF2013-11 pp.55-60 |
| RECONF | 2013-05-21 15:10 |
Kochi | Kochi Prefectural Culture Hall | Study of Runtime Binary Acceleration on TCA node Takaaki Miyajima, Takuya Kuhara (Keio Univ.), Toshihiro Hanawa (Univ. of Tsukuba), David Thomas (Imperial College), Hideharu Amano (Keio Univ.) RECONF2013-18 |
We are developing Toolchain and Domain Specific Language for Runtime Binary Acceleration, called Courier and Trailblaze... [more] |
RECONF2013-18 pp.97-102 |
| CPSY | 2012-10-12 11:10 |
Hiroshima | Study and Evaluation of Runtime Binary Acceleration Mechanism for OpenCV and GPU Takaaki Miyajima (Keio Univ.), David Thomas (Imperial), Hideharu Amano (Keio Univ.) CPSY2012-37 |
Runtime Binary Acceleration is a sort of acceleration such like that based on a analysis of running soft- ware binary (e... [more] | CPSY2012-37 pp.37-42 |
|
| DC, CPSY (Joint) |
2012-08-03 09:00 |
Tottori | Torigin Bunka Kaikan | Implementation of the circuit division for High-Level Synthesis Daiki Kugami, Takaaki Miyajima, Hideharu Amano (Keio Univ.) CPSY2012-18 |
High-Level Synthesis has been researched and developed for these 20 years. Not only ASIC, but also reconfigurable devic... [more] |
CPSY2012-18 pp.55-60 |
| RECONF | 2012-05-30 11:25 |
Okinawa | Tiruru (Naha Okinawa, Japan) | A Domain Specific Language and Toolchain for Runtime Binary Acceleration Takaaki Miyajima (Keio Univ.), David Thomas (Imperial), Hideharu Amano (Keio Univ.) RECONF2012-22 |
Computationally intensive applications can be off-loaded to FPGAs and GPUs to reduce execution time. However, choosing a... [more] | RECONF2012-22 pp.125-130 |
| CPSY, DC | 2012-04-10 13:50 |
Tokyo | The Automatic Code Optimization for High-Level Synthesis Mao Hatto, Takaaki Miyajima, Hideharu Amano (Keio Univ.) CPSY2012-3 DC2012-3 |
FPGA (Field Programmable Gate Array) has been applied to recent studies and products in high performance computation sys... [more] | CPSY2012-3 DC2012-3 pp.13-18 |
|
| RECONF | 2011-09-27 13:20 |
Aichi | Nagoya Univ. | Design and Implementation of Adaptive Viterbi Decoder using Dynamic Reconfigurable System STP Engine Yuken Kishimoto, Takao Toi, Takaaki Miyajima, Hideharu Amano (Keio Univ.) RECONF2011-38 |
Implementing Viterbi Algorithm that is the decoding method of Convolutional code on hard-wired logic, in order to variou... [more] | RECONF2011-38 pp.93-98 |
| RECONF | 2011-05-12 10:20 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Resource Sharing in FPGA and Implementation of Face-Angle Detection Algorithm using Impulse C Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic), Hideharu Amano (Keio Univ.) RECONF2011-1 |
Most of systems developed to prevent inattentive driving utilize a visible light camera with various processing algorith... [more] | RECONF2011-1 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 14:10 |
Fukuoka | Kyushu University | An FPGA Implementation of Face Detection Recognition System for automobile using Impulse C Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic), Hideharu Amano (Keio Univ.) RECONF2010-51 |
Since inattentive driving occupies $15\%$ of the cause of automobile accident, many companies are developing various sys... [more] | RECONF2010-51 pp.71-76 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] | 2010-03-26 11:55 |
Tokyo | An FPGA Implementation of Line-Based Architecture 2-Dimensional Discrete Wavelet Transform Using Impulse C Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic Kansei), Hideharu Amano (Keio Univ.) CPSY2009-84 DC2009-81 |
2 Dimensional DiscreteWavelet Transform(2D-DWT) that is used for Image compression on JPEG2000, makes theoretically less... [more] | CPSY2009-84 DC2009-81 pp.147-152 |
|
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-26 13:05 |
Kanagawa | Keio Univ (Hiyoshi Campus) | FPGA Implementation of Discrete Wavlet Transform Using Impulse C Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic Kansei), Hideharu Amano (Keio Univ.) VLD2009-75 CPSY2009-57 RECONF2009-60 |
Discrete Wavelet Transform(DWT), that is used for Image compression on JPEG2000, makes theoreticallyless noises than Dis... [more] | VLD2009-75 CPSY2009-57 RECONF2009-60 pp.35-40 |
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