Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF |
2023-06-08 16:00 |
Kochi |
Eikokuji Campus, Kochi University of Technology (Primary: On-site, Secondary: Online) |
Parallelization of Prim's Algorithm Using FPGA and Its Performance Evaluation Noritsune O, Kenji Kanazawa, Moritoshi Yasunaga (Univ. of Tsukuba) RECONF2023-3 |
A subgraph of an undirected graph G that is connected and contains no closed paths is called a tree, a global tree is a ... [more] |
RECONF2023-3 pp.13-16 |
DC, CPSY, IPSJ-ARC [detail] |
2021-10-11 10:00 |
Online |
Online |
A Study for Accelerating SpMV Using FPGA with High Bandwidth Memory Ryosuke Yanagisawa, Kenji Kanazawa, Moritoshi Yasunaga (University of Tsukuba) CPSY2021-12 DC2021-12 |
Sparse Matrix-Vector Multiplication (SpMV) is a fundamental operation that appears in various computer science applicati... [more] |
CPSY2021-12 DC2021-12 pp.1-6 |
EST |
2021-01-21 14:55 |
Online |
Online |
Simulation of Eye-diagram Based on Two-terminal-pair Network
-- Eye-diagram Computation Using Technical Formula Computing System -- Takahiko Kano, Moritoshi Yasunaga (Univ. Tsukuba) EST2020-61 |
An eye-diagram is one of the methods for the evaluation of signal integrity. The eye-diagram is measured by dividing a s... [more] |
EST2020-61 pp.45-50 |
RECONF |
2017-09-26 10:25 |
Tokyo |
DWANGO Co., Ltd. |
High-speed Calculation of k-means Clustering Using FPGA and its Application to Pick and Place Machine Shogo Nakamura, Hiroki Ebara, Kenji Kanazawa (Univ. of Tsukuba), Noriyuki Aibe (Keio Univ.), Moritoshi Yasunaga (Univ. of Tsukuba) RECONF2017-32 |
[more] |
RECONF2017-32 pp.57-62 |
R |
2015-11-19 14:25 |
Osaka |
|
A Measurement Method for the Extent of Simultaneous Soft Errors Noboru Masuda, Moritoshi Yasunaga (Univ. of Tsukuba) R2015-57 |
Regarding the LSI soft error caused by the neutron beam, a single particle of neutron may cause multiple chained soft er... [more] |
R2015-57 pp.5-10 |
RECONF |
2015-06-19 14:10 |
Kyoto |
Kyoto University |
High Speed Calculation of Convex Hull in 2D Images using FPGA Kahori Kemmotsu, Kenji Kanazawa, Yamato Mori (Univ. of Tsukuba), Noriyuki Aibe (SUSUBOX), Moritoshi Yasunaga (Univ. of Tsukuba) RECONF2015-7 |
Given a set of points, a convex hull is the smallest convex polygon containing all the points. In this paper, we describ... [more] |
RECONF2015-7 pp.35-40 |
VLD, CPSY, RECONF, IPSJ-SLDM [detail] |
2012-01-25 15:20 |
Kanagawa |
Hiyoshi Campus, Keio University |
A Proposal of Signal Integrity Improvement Method Using Impedance-reconfiguration Technique Moritoshi Yasunaga, Hiroki Shimada, Shohei Akita, Takuya Adachi, Hidetoshi Ishijima, Yusuke Kuribara (Univ. of Tsukuba) VLD2011-100 CPSY2011-63 RECONF2011-59 |
New techniques are strongly desired for signal integrity improvement on PCB traces in GHz-era because conventional imped... [more] |
VLD2011-100 CPSY2011-63 RECONF2011-59 pp.55-60 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-28 14:40 |
Miyazaki |
NewWelCity Miyazaki |
Waveform-Improvement of High-speed Signals on Branch Traces on PCBs Yusuke Kuribara, Shohei Akita, Hiroki Shimada, Takuya Adachi, Hidetoshi Ishijima (Univ. Tsukuba), Ikuo Yoshihara (Univ. Miyazaki), Moritoshi Yasunaga (Univ. Tsukuba) CPM2011-152 ICD2011-84 |
Recently, it is a serious problem that the signal integrity of high-speed signals transmitting on PCB traces deteriorate... [more] |
CPM2011-152 ICD2011-84 pp.19-24 |
RECONF |
2011-09-27 09:50 |
Aichi |
Nagoya Univ. |
A Basic Implementation of LUT-based Dynamic and Partial Reconfiguration from Remote Site Hiroyuki Kawai (Hamamatsu Photonics), Moritoshi Yasunaga (Tsukuba Univ.) RECONF2011-34 |
In this study we implement a mechanism that makes it possible to execute dynamic and partial reconfigurationfrom remote ... [more] |
RECONF2011-34 pp.69-74 |
RECONF |
2011-09-27 13:45 |
Aichi |
Nagoya Univ. |
Performance Comparison of the Pattern-Recognition Hardware Using Data-Direct-Implementation Approach Yusuke Sato, Moritoshi Yasunaga, Noriyuki Aibe (Univ. of Tsukuba) RECONF2011-39 |
We have proposed a novel architecture called “Direct Data Implementation (DDI)” aiming for a super high-speed recognitio... [more] |
RECONF2011-39 pp.99-104 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 11:40 |
Fukuoka |
Kyushu University |
Evaluation of Signal-Integrity Improvement Capability of the Segmental Transmission Line
-- In Its Application to Lines Including Inductances -- Hiroki Shimada, Shohei Akita, Masami Ishiguro, Moritoshi Yasunaga, Noriyuki Aibe (Univ. of Tsukuba), Ikuo Yoshihara (Univ. of Miyazaki) CPM2010-127 ICD2010-86 |
In recent years, signal integrity(SI) is becoming very serious problem in the area of transmitting high-frequency-digita... [more] |
CPM2010-127 ICD2010-86 pp.19-24 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 10:10 |
Fukuoka |
Kyushu University |
Reliable Digital Signal Transmission Methodology
-- Its Application to the High Speed Bass Line -- Shohei Akita, Hiroki Shimada, Masami Ishiguro, Noriyuki Aibe, Moritoshi Yasunaga (Univ. of Tsukuba), Ikuo Yoshihara (Miyazaki Univ.) CPSY2010-38 |
[more] |
CPSY2010-38 pp.37-42 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 09:30 |
Fukuoka |
Kyushu University |
Power-Consumption-Evaluation on the Pattern-Recognition Machine Using Data-Direct-Implementation Approach Yusuke Sato, Moritoshi Yasunaga, Noriyuki Aibe (Univ. of Tsukuba) RECONF2010-44 |
[more] |
RECONF2010-44 pp.31-36 |
RECONF |
2010-09-16 11:00 |
Shizuoka |
Shizuoka University (Faculty of Eng., Hall 2) |
Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration Hiroyuki Kawai, Moritoshi Yasunaga (Tsukuba Univ.) RECONF2010-18 |
In this paper, we develop an on-chip pattern recognition system.
The feature of this system is that two Microblaze core... [more] |
RECONF2010-18 pp.1-6 |
CPM |
2010-07-29 15:20 |
Hokkaido |
Michino-Eki Shari Meeting Room |
Proposal and Experimental Evaluation of A Novel Method for Eye-Pattern Improvement on Transmission Lines Masami Ishiguro, Yuki Shimauchi, Noriyuki Aibe (Tsukuba Univ.), Ikuo Yoshihara (Miyazaki Univ.), Moritoshi Yasunaga (Tsukuba Univ.) CPM2010-34 |
Recently GHz frequency signal is required to be propagated in the PCB (printed circuit board) with low distortions. To o... [more] |
CPM2010-34 pp.17-22 |
RECONF |
2010-05-14 10:20 |
Nagasaki |
|
A study of a single-instruction variable-data processor on an FPGA Syoji Tanabe, Yoshiki Yamaguchi, Moritoshi Yasunaga (Univ. of Tsukuba) |
[more] |
|
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 10:40 |
Kochi |
Kochi City Culture-Plaza |
Evaluation of Waveform-Improvement performance on the Segmental Transmission Line Yuki Shimauchi, Hiroshi Nakayama, Yoshiki Yamaguchi, Noriyuki Aibe (Tsukuba Univ.), Ikuo Yoshihara (Miyazaki Univ.), Moritoshi Yasunaga (Tsukuba Univ.) CPM2009-145 ICD2009-74 |
As processor-speed increases, high-speed signal-propagation in the PCB traces following the processor-speed is also requ... [more] |
CPM2009-145 ICD2009-74 pp.63-68 |
RECONF |
2009-05-15 12:40 |
Fukui |
|
* Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Tsukuba Univ.) RECONF2009-13 |
In this paper, we extend DDI (Direct Data Implementation), that is pattern data are directly transformed into logic circ... [more] |
RECONF2009-13 pp.73-78 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 13:25 |
Fukuoka |
Kitakyushu Science and Research Park |
An Adaptive Pattern Recognition hardware with On-chip Dynamic and Partial Reconfiguration Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Tsukuba Univ.), Kyrre Glette, Jim Toressen (Oslo Univ.) RECONF2008-50 |
A pattern recognition system that can process a
large amount of image data at high speed is required
in many fields. I... [more] |
RECONF2008-50 pp.63-68 |
RECONF |
2008-09-26 13:20 |
Okayama |
Okayama Univ. |
A study of a fault-tolerant System using TFT method Atsuhiro Kanamaru, Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Univ. of Tsukuba) RECONF2008-36 |
This paper deals with a dependable computing system using a reconfigurable device. The work carried out for this purpos... [more] |
RECONF2008-36 pp.81-86 |