IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 21  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2023-04-11
13:20
Kanagawa
(Primary: On-site, Secondary: Online)
[Invited Talk] Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating
Yuto Yakubo, Kazuma Furutani, Kouhei Toyotaka, Haruki Katagiri, Masashi Fujita, Munehiro Kozuma, Yoshinori Ando, Yoshiyuki Kurokawa (SEL), Toru Nakura (Fukuoka Univ.), Shunpei Yamazaki (SEL) ICD2023-10
We have achieved a small-area, low-power AI chip that enables inference corresponding to multiple neural networks using ... [more] ICD2023-10
pp.18-23
SDM 2022-01-31
15:30
Online Online [Invited Talk] Novel Analog in-Memory Computing with < 1nA Current/Cell and 143.9 TOPS/W Enabled by Monolithic Normally-off Zn-rich CAAC-IGZO FET-on-Si CMOS Technology
Yoshiyuki Kurokawa, Haruyuki Baba, Satoru Ohshita, Toshiki Hamada, Yoshinori Ando, Ryota Hodo, Toshikazu Ono, Takashi Hirose, Hitoshi Kunitake, Tsutomu Murakawa (Semiconductor Energy Lab.), Toru Nakura (Fukuoka Univ.), Masaharu Kobayashi (Tokyo Univ.), Hiroshi Yoshida, Min-Cheng Chen (PSMC), Ming-Han Liao (National Taiwan Univ.), Shou-Zen Chang (PSMC), Shunpei Yamazaki (Semiconductor Energy Lab.) SDM2021-72
We have successfully demonstrated high-efficiency analog in-memory computing (AiMC) chips, which are monolithically fabr... [more] SDM2021-72
pp.16-19
ICD, CPSY, CAS 2017-12-14
09:50
Okinawa Art Hotel Ishigakijima Design of Quick-Lock Reference-Clock-Less All-Digital CDR using Delay Tunable Buffer for Lock Range Extension
Meikan Chin, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) CAS2017-64 ICD2017-52 CPSY2017-61
A quick-lock reference-clock-less all-digital burst-mode CDR is proposed. Since the proposed CDR resumes from a standby ... [more] CAS2017-64 ICD2017-52 CPSY2017-61
pp.3-8
ICD, CPSY, CAS 2017-12-14
10:10
Okinawa Art Hotel Ishigakijima Design of Non-Binary SAR ADC with Noise-Tunable Comparator
Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (The Univ. of Tokyo) CAS2017-65 ICD2017-53 CPSY2017-62
A 16-bit non-binary SAR ADC with a noise-tunable comparator for low power consumption is presented. A non-binary-weight... [more] CAS2017-65 ICD2017-53 CPSY2017-62
pp.9-13
ICD, CPSY, CAS 2017-12-14
10:40
Okinawa Art Hotel Ishigakijima Performance Analysis of Level-Cross Detection Method based on Stochastic Comparator
Taiki Sugiyama, Tetsuya Iizuka (Univ. of Tokyo), Takahiro Yamaguchi (Advantest), Toru Nakura, Kunihiro Asada (Univ. of Tokyo) CAS2017-66 ICD2017-54 CPSY2017-63
ADC based on level-cross detection quantizes time rather than voltage. When the clock frequency is doubled, SNR of ADC i... [more] CAS2017-66 ICD2017-54 CPSY2017-63
pp.15-20
ICD, CPSY 2015-12-18
15:55
Kyoto Kyoto Institute of Technology Performance Analysis of Analog to Digital Converter Based on Stochastic Comparator
Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Tokyo University) ICD2015-93 CPSY2015-106
A performance model for Analog to Digital Converter (ADC) based on stochastic comparator has been proposed by analyzing ... [more] ICD2015-93 CPSY2015-106
pp.123-128
ICD, CPSY 2015-12-18
16:20
Kyoto Kyoto Institute of Technology A Time-Mode Analog Signal Accumulator Using a Single Buffer Ring without Output Drift Calibration
Tomohiko Yano, Toru Nakura, Testuya Iizuka, Kunihiro Asada (Univ. of Tokyo) ICD2015-94 CPSY2015-107
This paper presents a time-mode analog signal accumulator whose input and output are both represented by the time differ... [more] ICD2015-94 CPSY2015-107
pp.129-134
ICD, CPSY 2015-12-18
16:45
Kyoto Kyoto Institute of Technology Autonomously Tracking PVT Variations of Pulse Width Controlled PLL using Hill-Climbing Method
Toi Takashi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada (Tokyo Univ.) ICD2015-95 CPSY2015-108
 [more] ICD2015-95 CPSY2015-108
pp.135-140
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
14:10
Nagasaki Nagasaki Kinro Fukushi Kaikan A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique
Norihito Tohge, Tetsuya Iizuka, Toru Nakura (Univ. of Tokyo), Satoshi Miura, Yoshimichi Murakami (THine), Kunihiro Asada (Univ. of Tokyo) CPM2015-130 ICD2015-55
A quick-lock all-digital Clock-Data Recovery circuit that does not require a reference clock is propposed. Internal
Tim... [more]
CPM2015-130 ICD2015-55
pp.17-22
ICD, IE, VLD, IPSJ-SLDM [detail] 2015-10-26
15:00
Miyagi   Design of Fine-Resolution Pulse Shrinking Time-to-Digital Converter
Takehisa Koga, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) VLD2015-29 ICD2015-42 IE2015-64
A pulse-shrinking Time-to-Digital Converter (TDC) with an offset pulse width detection scheme is presented. In the conve... [more] VLD2015-29 ICD2015-42 IE2015-64
pp.13-18
ICD, CPSY 2014-12-02
16:05
Tokyo Kikai-Shinko-Kaikan Bldg. An accelerating method of NBTI degradation transition analysis based on logic simulation
Kazunori Mori, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada (UTokyo) ICD2014-109 CPSY2014-121
Negative Bias Temperature Instability (NBTI) degradation is one of the important problems in nano-scale transistors.In t... [more] ICD2014-109 CPSY2014-121
pp.141-145
ICD, ITE-IST 2011-07-22
09:50
Hiroshima Hiroshima Institute of Technology On-Chip Resonant Supply Noise Reduction Using Active Decoupling Capacitors
Jinmyoung Kim (Tokyo Univ.), Toru Nakura (VDEC), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (VDEC) ICD2011-27
 [more] ICD2011-27
pp.69-72
ITS, IE, ITE-AIT, ITE-HI, ITE-ME [detail] 2011-02-21
13:15
Hokkaido Hokkaido University Overlay Coding for Visible Light Communication using LED Array and High-Speed Camera
Sayaka Nishimoto, Toru Nagura, Takaya Yamazato, Tomohiro Yendo (Nagoya Univ.), Toshiaki Fujii (Tokyo Inst. of Tech.), Hiraku Okada (Saitama Univ.), Shintaro Arai (Aichi Univ. of Tech.) ITS2010-39 IE2010-114
In this paper, we discuss on visible light communications using an LED array as the transmitter and a highspeed camera a... [more] ITS2010-39 IE2010-114
pp.89-94
ITS, IE, ITE-AIT, ITE-HI, ITE-ME [detail] 2011-02-21
13:40
Hokkaido Hokkaido University Performance Improvement with the Inverted Signal to Track an LED Array Transmitter on Road-to-Vehicle Visible Light Communications
Toru Nagura, Takaya Yamazato, Tomohiro Yendo (Nagoya Univ.), Toshiaki Fujii (Tokyo Inst. of Tech.), Hiraku Okada (Saitama Univ.) ITS2010-40 IE2010-115
 [more] ITS2010-40 IE2010-115
pp.95-99
ICD 2010-12-17
09:30
Tokyo RCAST, Univ. of Tokyo [Invited Talk] Time Difference Amplifier, from Getting Idea to Presenting at a Conference
Toru Nakura (Univ. of Tokyo) ICD2010-117
 [more] ICD2010-117
pp.107-111
ICD, SDM 2010-08-26
09:10
Hokkaido Sapporo Center for Gender Equality On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks
Jinmyoung Kim, Toru Nakura (Univ. of Tokyo.), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) SDM2010-124 ICD2010-39
This paper proposes an on-chip supply resonance noise reduction method for multi-IP cores utilizing parasitic capacitanc... [more] SDM2010-124 ICD2010-39
pp.1-4
ICD, ITE-IST 2010-07-22
10:45
Osaka Josho Gakuen Osaka Center Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect
Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) ICD2010-24
In this paper, we propose an all-digital process variability monitor which utilizes a simple buffer ring with a pulse co... [more] ICD2010-24
pp.15-20
ITE-AIT, IE, ITE-HI, ITE-ME, ITS 2010-02-15
15:50
Hokkaido Graduate School of Information and Technology, Hokkaido Univ. Successive Interference Cancellation for Hierarchical Coding in Optical Wireless Communication Systems using LED array and High speed camera
Toshiyuki Ozawa, Toru Nagura, Takaya Yamazato, Masaaki Katayama, Tomohiro Yendo (Nagoya Univ.), Toshiaki Fujii (Tokyo Inst. of Tech.), Hiraku Okada (Saitama Univ.) ITS2009-46 IE2009-140
We propose a successive interference cancellation scheme (SIC) for the hierarchical coding parallel optical communicatio... [more] ITS2009-46 IE2009-140
pp.53-58
ITE-AIT, IE, ITE-HI, ITE-ME, ITS 2010-02-15
16:15
Hokkaido Graduate School of Information and Technology, Hokkaido Univ. Detection and Tracking of LED Array Transmitter for Visible Light Communications on Driving Situation
Toru Nagura, Toshiyuki Ozawa, Takaya Yamazato, Masaaki Katayama, Tomohiro Yendo (Nagoya Univ.), Toshiaki Fujii (Tokyo Inst. of Tech.), Hiraku Okada (Saitama Univ.) ITS2009-47 IE2009-141
In this paper, we discuss on a decoding algorithm for visible light communication systems on driving situation using a L... [more] ITS2009-47 IE2009-141
pp.59-64
ICD, ITE-IST 2009-10-02
09:10
Tokyo CIC Tokyo (Tamachi) Study of Active Substrate Noise Cancelling Technique using PowerLine di/dt Detector
Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) ICD2009-46
This paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time diff... [more] ICD2009-46
pp.69-73
 Results 1 - 20 of 21  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan