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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2016-02-17 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An RTL Test Point Insertion Method to Reduce the Number of Test Patterns Naoya Ohsaki, Toshinori Hosokawa, Hiroshi Yamazaki (NU), Masayoshi Yoshimura (KSU)  DC2015-93 |
Test point insertion methods to reduce the number of test patterns have been proposed for test cost reduction of VLSIs. ... [more] | DC2015-93 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 13:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | An M by N Algorithm Using Multiple Target Test Generation for Static Test Compaction Yuya Hara, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon University), Masayoshi Yoshimura (Kyoto Sangyo university) VLD2015-69 DC2015-65 |
[more] | VLD2015-69 DC2015-65 pp.207-212 |
| DC | 2015-06-16 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A test data reduction method based on scan slice on BAST Makoto Nishikiori, Hiroshi Yamazaki, Toshinori Hosokawa, Masayuki Arai (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2015-16 |
BAST is one of techniques to reduce the amount of test data while maintaining high test quality by combining built-in se... [more] | DC2015-16 pp.1-6 |
| DC | 2015-02-13 11:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg | A Hardware Trojan Circuit Detection Method Based on Information of Nontransitional Lines Tomohiro Bouyashiki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (KUS) DC2014-81 |
[more] | DC2014-81 pp.19-24 |
| DC | 2015-02-13 11:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Test Method for Encryption LSI against Scan-based Attacks Masayoshi Yoshimura (Kyoto Sangyo Univ.), Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.) DC2014-82 |
[more] | DC2014-82 pp.25-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:05 |
Oita | B-ConPlaza | A Test Point Insertion Method to Reduce Capture Power Dissipation Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) VLD2014-99 DC2014-53 |
In at-speed scan testing of deep sub-micron era, high power dissipation can occur by high launch-induced switching activ... [more] | VLD2014-99 DC2014-53 pp.185-190 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:30 |
Oita | B-ConPlaza | A Multi Cycle Capture Test Generation Method to Reduce Capture Power Dissipation Hiroshi Yamazaki, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) VLD2014-100 DC2014-54 |
[more] | VLD2014-100 DC2014-54 pp.191-196 |
| DC | 2014-02-10 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Low Power Dissipation Oriented Don't Care Filling Method Using SAT Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ) DC2013-83 |
High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captur... [more] | DC2013-83 pp.25-30 |
| DC | 2014-02-10 15:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A reduction method of shift data volume on BAST Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ) DC2013-87 |
BAST is one of techniques to reduce the amount of test data while maintaining the high test quality using built-in self ... [more] | DC2013-87 pp.49-54 |
| DC | 2014-02-10 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Low Power Consumption Oriented Test Generation Method for Transition Faults Using Multi Cycle Capture Test Generation Hiroshi Yamazaki, Yuto Kawatsure, Jun Nishimaki, Atsushi Hirai, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Koji Yamazaki (Meiji Univ) DC2013-89 |
High power dissipation can occur when the response to a test pattern is captured by flip-flops in at-speed scan testing,... [more] | DC2013-89 pp.61-66 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 14:10 |
Kagoshima | An inverter block construction method to reduce test data volume on BAST Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ), Michinobu Nakao (Yomiuri Institute) VLD2013-85 DC2013-51 |
BAST is one of technique to reduce the amount of test data while maintaining the high test quality using built-in self t... [more] | VLD2013-85 DC2013-51 pp.171-176 |
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| DC | 2013-02-13 11:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A don't care filling method to improve defect detection capability using stuck-at fault test sets and transition fault test sets Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ) DC2012-83 |
[more] | DC2012-83 pp.19-24 |
| DC | 2013-02-13 14:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An evaluation of Trojan Circuits on AES Encryption Circuits Amy Ogita, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2012-86 |
[more] | DC2012-86 pp.37-42 |
| DC | 2013-02-13 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Evaluatoin Method of Test Compactors for Secure Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) DC2012-87 |
[more] | DC2012-87 pp.43-47 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 15:20 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A don't care filling method improve fault sensitization coverage on transition fault test set Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ) VLD2012-103 DC2012-69 |
[more] | VLD2012-103 DC2012-69 pp.255-260 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 16:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Study on Test Generation for Effective Test Compaction Yukino Kusuyama, Tatuya Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) VLD2012-105 DC2012-71 |
In recent year, the numbers of target fault models and faults for testing increase because the number of gates on VLSIs ... [more] | VLD2012-105 DC2012-71 pp.267-272 |
| VLD, CAS, MSS, SIP | 2012-07-02 14:10 |
Kyoto | Kyoto Research Park | An Evaluation of Heuristic Fault Simulation Algorithms for Transient Faults in Sequential Circuits Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) CAS2012-10 VLD2012-20 SIP2012-42 MSS2012-10 |
[more] | CAS2012-10 VLD2012-20 SIP2012-42 MSS2012-10 pp.55-60 |
| DC | 2012-06-22 13:00 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | An evaluation of a don't care filling method to improve fault sensitization coverage Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ) DC2012-9 |
A single stuck-at fault model and a transition fault model have been widely used to generate test patterns for VLSIs. Ho... [more] | DC2012-9 pp.1-6 |
| DC | 2012-02-13 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Evaluation of the Effects for Hardware Trojan Designs in AES Encryption Circuits Amy Ogita, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2011-77 |
[more] | DC2011-77 pp.7-12 |
| DC | 2012-02-13 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A method to reduce the number of test patterns for transition faults using control point insertions Akihiko Takahashi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) DC2011-82 |
In recent year, the growing density and complexity for VLSIs cause an increase in the number of test patterns. Moreover,... [more] | DC2011-82 pp.37-42 |
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