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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-26 11:40 |
Online | Online | A Controller Augmentation method to Improving Transition Fault Coverage Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ)  CPSY2020-63 DC2020-93 |
With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern VLSIs are increasin... [more] | CPSY2020-63 DC2020-93 pp.79-84 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-26 12:00 |
Online | Online | A Logic Locking Method Based on Anti-SAT at Register Transfer Level Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-64 DC2020-94 |
In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design... [more] | CPSY2020-64 DC2020-94 pp.85-90 |
| DC | 2021-02-05 14:00 |
Online | Online | Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74 |
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] | DC2020-74 pp.30-35 |
| DC | 2021-02-05 15:30 |
Online | Online | A Don't Care Filling Method of Control Signals Based on Non-scan Field Testability at Register Transfer Level Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2020-77 |
A field testing that monitors the values of circuit outputs and internal signal lines during function mode is used as on... [more] | DC2020-77 pp.48-53 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 15:45 |
Online | Online | A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12 |
In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] | CPSY2020-12 DC2020-12 pp.75-80 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 17:30 |
Online | Online | An Area Reduction Oriented Controller Augmentation Method Based on Functionally Equivalent Finite State Machine Generation Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-15 DC2020-15 |
In recent year, controller augmentation has been used for design-for-testability and design-for-security at register tra... [more] | CPSY2020-15 DC2020-15 pp.93-98 |
| HWS, VLD [detail] | 2020-03-06 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | VLD2019-131 HWS2019-104 pp.215-220 |
| DC | 2020-02-26 12:00 |
Tokyo | A controller augmentation method to reduce the number of untestable faults for multiplexers with n-inputs Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2019-90 |
With the complexity for VLSIs, transition fault testing is required. However, VLSIs generally have more untestable trans... [more] | DC2019-90 pp.25-30 |
|
| DC | 2020-02-26 14:10 |
Tokyo | A Don’t Care Identification-Filling Co-Optimization Method for Low Power Testing Using Partial Max-SAT Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2019-92 |
Recently, in at-speed scan testing, excessive capture power dissipation is a serious problem. Low capture power test gen... [more] | DC2019-92 pp.37-42 |
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| DC, SS | 2019-10-24 16:00 |
Kumamoto | Kumamoto Univ. | A Non-scan Online Test Based on Covering n-Time State Transition Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) SS2019-19 DC2019-47 |
As one of the means to avoid the fault due to the deteriorate over time of VLSI, online test is used to monitor the outp... [more] | SS2019-19 DC2019-47 pp.37-42 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 09:00 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) CPSY2018-117 DC2018-99 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | CPSY2018-117 DC2018-99 pp.315-320 |
| DC | 2019-02-27 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Low Capture Power Oriented X-Identification Method Mimicking Fault Propagation Paths of Capture Safe Test Vectors Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ) DC2018-73 |
Low power oriented don't care (X) identification and X filling methods have been proposed to reduce the numbers of captu... [more] | DC2018-73 pp.13-18 |
| DC | 2019-02-27 13:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | State Assignment Method to Improve Transition Fault Coverage for Datapath Masayoshi Yoshimura (Kyoto Sangyo Univ.), Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.) DC2018-78 |
Recently, it is indispensable to test in transition fault model due to timing defects increase along with complication a... [more] | DC2018-78 pp.43-48 |
| HWS, VLD | 2019-03-01 12:40 |
Okinawa | Okinawa Ken Seinen Kaikan | On evaluation of an efficient SAT attack algorithm for logic encryption Yusuke Matsunaga (Kyushu Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2018-126 HWS2018-89 |
[more] | VLD2018-126 HWS2018-89 pp.199-204 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:00 |
Hiroshima | Satellite Campus Hiroshima | An efficient SAT-attack algorithm against logic encryption Yusuke Matsunaga (Kyushu Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) VLD2018-60 DC2018-46 |
[more] | VLD2018-60 DC2018-46 pp.143-148 |
| DC | 2018-02-20 09:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2017-78 |
It is required to reduce the number of test patterns to reduce test cost for VLSIs. Especially, design-for-testability m... [more] | DC2017-78 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | An Evaluation for the Number of Decoding Key for Logic Encryption Methods for IP Cores Hashidate Hidemi, Hosokawa Toshinori (Nihon Univ.), Yoshimura Masayoshi (Kyoto Sangyo Univ.) VLD2017-31 DC2017-37 |
[more] | VLD2017-31 DC2017-37 pp.25-30 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) VLD2017-37 DC2017-43 |
Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the incr... [more] | VLD2017-37 DC2017-43 pp.61-66 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 14:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Detection Method for Trojan Circuit inserted in Manufacturing Process Yoshinobu Okuda, Masayoshi Yoshimura, Kohei Ohyama (Kyoto Sangyo Univ.) VLD2017-53 DC2017-59 |
[more] | VLD2017-53 DC2017-59 pp.145-150 |
| DC | 2017-02-21 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States Morito Niseki, Toshinori Hosokawa (Nihon Univ.), Msayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2016-79 |
Scan design has problems such as large hardware overhead and long test application time. Non-scan based test generation ... [more] | DC2016-79 pp.29-34 |
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