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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 89  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2024-02-28
14:05
Tokyo Kikai-Shinko-Kaikan Bldg. A Low Power Oriented Multiple Target Test Generation Method for 2 Cycle Gate-Exhaustive Faults Using Pseudo Boolean Optimization
Momona Mizota, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyou Uni), Masayuki Arai (Nihon Univ) DC2023-99
 [more] DC2023-99
pp.29-34
DC 2024-02-28
15:40
Tokyo Kikai-Shinko-Kaikan Bldg. On Additional Status Signal Sequences Generation to Improve Estimated Field Random Testability for Datapaths at Register Transfer Level
Yudai Toyooka, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2023-102
 [more] DC2023-102
pp.47-52
DC 2023-12-08
13:50
Nagasaki ARKAS SASEBO
(Primary: On-site, Secondary: Online)
A Multiple Target Seed Generation Method for Random Pattern Resistant Faults Using a Compatible Fault Set on Built-in Self Test
Takanobu Sone, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) DC2023-88
In recent years, with high density of very large-scale integrated circuits, it has become impractical to store a large n... [more] DC2023-88
pp.7-12
CPSY, DC, IPSJ-ARC [detail] 2023-08-03
10:55
Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)
An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing
Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) CPSY2023-11 DC2023-11
 [more] CPSY2023-11 DC2023-11
pp.19-24
CPSY, DC, IPSJ-ARC [detail] 2023-08-03
11:20
Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)
A Don't Care Filling Method of Control Signals in Controllers to Maximize the Number of Distinguishable Weighted Hardware Element Pairs
Yui Otsuka, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Koji Yamazaki (Meiji Univ.) CPSY2023-12 DC2023-12
 [more] CPSY2023-12 DC2023-12
pp.25-30
HWS, VLD 2023-03-03
11:50
Okinawa
(Primary: On-site, Secondary: Online)
A Seed Selection Method to Minimize Test Application Time for Logic BIST Using Pseudo Boolean Optimization
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2022-105 HWS2022-76
 [more] VLD2022-105 HWS2022-76
pp.173-178
HWS, VLD 2023-03-03
13:50
Okinawa
(Primary: On-site, Secondary: Online)
A Logic Locking Method based on Function Modification Circuit
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.) VLD2022-107 HWS2022-78
In recent years, with the increase of VLSI integration, semiconductor design companies to design a VLSI have tended to u... [more] VLD2022-107 HWS2022-78
pp.185-190
DC 2023-02-28
14:50
Tokyo Kikai-Shinko-Kaikan Bldg
(Primary: On-site, Secondary: Online)
A Don't-Care Filling Method of Control Signals on Controllers for Two-Pattern Concurrent Testing
Xu Haofeng, Hosokawa Toshinori (Nihon Univ.), Yoshimura Masayoshi (KSU), Arai Masayuki (Nihon Univ.) DC2022-88
 [more] DC2022-88
pp.33-38
DC 2023-02-28
15:15
Tokyo Kikai-Shinko-Kaikan Bldg
(Primary: On-site, Secondary: Online)
A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for BIST
Yangling Xu, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (KSU) DC2022-89
With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern very large integrat... [more] DC2022-89
pp.39-44
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-29
10:05
Kumamoto  
(Primary: On-site, Secondary: Online)
A Seed Generation Method for Multiple Random Pattern Resistant Stuck-at Faults in Built-In Self-Test
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2022-27 ICD2022-44 DC2022-43 RECONF2022-50
 [more] VLD2022-27 ICD2022-44 DC2022-43 RECONF2022-50
pp.49-54
CPSY, DC, IPSJ-ARC [detail] 2022-10-12
14:00
Niigata Yuzawa Toei Hotel
(Primary: On-site, Secondary: Online)
A Don't Care Filling Algorithm of Control Signals for Concurrent Testing
Xu Haofeng, Hosokawa Toshinori (Nihon Univ.), Yoshimura Masayoshi (KSU), Arai Masayuki (Nihon Univ.) CPSY2022-24 DC2022-24
In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. ... [more] CPSY2022-24 DC2022-24
pp.37-42
CPSY, DC, IPSJ-ARC [detail] 2022-07-27
09:45
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)

Enrei Jo, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayosi Yoshimura (KSU) CPSY2022-1 DC2022-1
In recent years, with the low power design of VLSIs, many low power oriented don't care (X) identification methods and X... [more] CPSY2022-1 DC2022-1
pp.1-6
CPSY, DC, IPSJ-ARC [detail] 2022-07-27
10:15
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
On the Acceleration of a Low Power Oriented Test Generation Method Using Fault Excitation Conditions
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) CPSY2022-2 DC2022-2
 [more] CPSY2022-2 DC2022-2
pp.7-12
CPSY, DC, IPSJ-ARC [detail] 2022-07-27
11:00
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
A Block Partitioning Method to Accelerate Test Generation for Gate-Exhaustive Faults
Momona Mizota, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) CPSY2022-3 DC2022-3
In gate-exhaustive fault model which covers defects in cells, since the number of faults is proportion to that of gates,... [more] CPSY2022-3 DC2022-3
pp.13-18
CPSY, DC, IPSJ-ARC [detail] 2022-07-27
11:30
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
An Evaluation of Field Testability Using States Signal Sequences Based on k-Consecutive State Transitions for Field Testing
Yudai Toyooka, Yuki Watanabe, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2022-4 DC2022-4
 [more] CPSY2022-4 DC2022-4
pp.19-24
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
10:30
Online Online A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing
Haofeng Xu, Toshinori Hosokawa, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ), Masayoshi Yoshimura (KSU) CPSY2021-56 DC2021-90
In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. ... [more] CPSY2021-56 DC2021-90
pp.67-72
DC 2022-03-01
13:45
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
A Logic Locking Method based on SFLL-hd at Register Transfer Level
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) DC2021-72
In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called ... [more] DC2021-72
pp.45-50
DC 2022-03-01
15:10
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
State assignment method to improve transition fault coverage for controllers including invalid states
Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) DC2021-75
 [more] DC2021-75
pp.63-68
DC 2021-12-10
13:00
Kagawa
(Primary: On-site, Secondary: Online)
A Low Power Oriented Multiple Target Test Generation Method
Rei Miura, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) DC2021-55
In recent years, since capture power consumption for VLSIs significantly increases in at-speed scan testing, low capture... [more] DC2021-55
pp.1-6
DC 2021-12-10
14:00
Kagawa
(Primary: On-site, Secondary: Online)
A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2021-57
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design co... [more] DC2021-57
pp.13-18
 Results 1 - 20 of 89  /  [Next]  
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