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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2010-09-27
16:30		 Kyoto Kyoto Institute of Technology [Invited Talk] An Automatic Test Generation Framework for Digitally-Assisted Analog Circuit
Satoshi Komatsu, Mohamed Abbas (Univ. of Tokyo), Yasuo Furukawa (Advantest), Kunihiro Asada (Univ. of Tokyo) VLD2010-46		 This paper presents a new analog ATPG (AATPG) framework that generates near-optimal test stimulus for the digitally-assi... [more] VLD2010-46
pp.25-30
ICD, CPM 2005-01-28
16:15		 Tokyo Kikai-Shinko-Kaikan Bldg. New SoC Testing technologies for beyond 65nm process rule -- New Failure Analysis and Testing methodologies for low-k/Cu Interconnect technique --
Makoto Yamazaki, Yasuo Furukawa (ADVANTEST) 		To solve the problems such as the yield improvements and securing the test quality in the SoC devices made efficient, th... [more] CPM2004-173 ICD2004-218
pp.65-70
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