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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2009-04-13
14:30		 Miyagi Daikanso (Matsushima, Miyagi) [Invited Talk] MRAM technology trend and evolution, 32Mb MRAM development
Tadahiko Sugibayashi, Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito (NEC), Yuichi Ito (NECEL), Sadahiko Miura, Yuko Kato, Kaoru Mori (NEC), Yasuaki Ozaki, Yosuke Kobayashi (NECEL), Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara (NEC) ICD2009-3		  [more] ICD2009-3
pp.13-17
ICD 2008-04-18
13:55		 Tokyo   A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme
Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-12		 We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) a... [more] ICD2008-12
pp.63-68
ICD 2008-04-18
14:20		 Tokyo   A 250-MHz 1-Mbit Embedded MRAM Macro Using 2T1MTJ Cell with Bitline Separation and Half-pitch Shift Architecture
Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-13		 A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-um standard CMOS process with 1.5V supply. Its clock frequency is ... [more] ICD2008-13
pp.69-74
ICD 2006-04-14
09:30		 Oita Oita University a 4Mb MRAM and its experimental application
Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Kiyokazu Nagahara, Sadahiko Miura, Ken-ichi Shimura, Kiyotaka Tsuji, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Yuko Kato, Shinsaku Saito, Naoki Kasai, Hideaki Numata, Norikazu Ohshima (NEC) 		The memory-cell technology, circuit technology and fabrication results of a newly developed 4Mb MRAM and an application ... [more] ICD2006-12
pp.63-67
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