| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2018-04-20 14:55 |
Tokyo | [Invited Talk]
Design and Development of a memory-based reconfigurable logic device Mamoru Ohara (TIRI), Masayuki Sato (TRL), Tadashi Okabe (TIRI), Mitsunori Katsu (TRL)  ICD2018-13 |
[more] | ICD2018-13 pp.53-54 |
|
| WIT, IPSJ-AAC | 2018-03-10 15:50 |
Ibaraki | Tsukuba University of Technology | Discussion on Development of E-learning System for Deafblind College Students(part2)
-- Information Accessibility Using Braille Terminal and Real Time Captioning Support in a Lecture -- Manabi Miyagi, Masayuki Sato (NTUT) WIT2017-90 |
he purpose of this sturdy was to develop E-learning system on working with deafblind college students. In this paper, we... [more] | WIT2017-90 pp.193-196 |
| WIT, IPSJ-AAC | 2018-03-10 16:10 |
Ibaraki | Tsukuba University of Technology | Working with Deafblind Student on Study Life in Higher Education Institution Masayuki Sato, Manabi Miyagi, Mayumi Shirasawa (NTUT) WIT2017-91 |
In this paper, we report on working with the Deafblind student on study life in higher education institution. We discuss... [more] | WIT2017-91 pp.197-200 |
| DC | 2018-02-20 16:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD) Senling Wang, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Masayuki Sato, Mitsunori Katsu (TRL), Shoichi Sekiguchi (TAIYOYUDEN) DC2017-87 |
MRLD is a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In order to... [more] | DC2017-87 pp.61-66 |
| ET | 2017-01-28 11:55 |
Kanagawa | National Institute of Special Needs Education | Discussion on Development of E-learning System for Deafblind College Students
-- Information Accessibility Using Braille Terminal and Real Time Captioning Support in a Lecture -- Manabi Miyagi, Masayuki Sato, Masayuki Kobayashi (Tsukuba Univ.Tech.) ET2016-84 |
The purpose of this sturdy was to develop E-learning system on working with deafblind college students. In this paper, w... [more] | ET2016-84 pp.35-38 |
| ET | 2017-01-28 14:10 |
Kanagawa | National Institute of Special Needs Education | Study on a Virtual Resource Room for Deaf or Hard of Hearing Children in an Inclusive Educational Environment Yasushi Ishihara, Masayuki Sato, Shigeki Miyoshi, Tomoyuki Nishioka (NTUT) ET2016-87 |
Based on the study carried out in 2009-2012, we started the research on a virtual resource room from 2013. A virtual res... [more] | ET2016-87 pp.49-52 |
| SP, WIT | 2013-06-13 17:00 |
Niigata | Sound localization under amplification Tatsuo Nakagawa (YNU), Masayuki Sato (Tsukuba Univ. Tech.), Masahiro Takahashi (Yokohama City Univ.) SP2013-41 WIT2013-11 |
A sound localization test was administered to people with normal hearing and hearing-impairment. We measured sound local... [more] | SP2013-41 WIT2013-11 pp.61-64 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 15:25 |
Kanagawa | Hiyoshi Campus, Keio University | Evaluation of Improvement Techniques for Placement and Routing on MPLD : a New Reconfigurable Device Ken Taomoto, Masato Inagi, Hideyuki Kawabata, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura, Masatoshi Nakamura (Hiroshima City Univ) |
(To be available after the conference date) [more] | |
| RECONF | 2011-09-26 11:10 |
Aichi | Nagoya Univ. | Feasibility study of nonvolatile reconfiguralbe device by using a standard CMOS logic process Shuji Kunimitsu, Mamoru Terauchi, Kazuya Tanigawa, Tetsuo Hironaka (HCU), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN) RECONF2011-23 |
In this paper, we consider the realization of nonvolatile PLD, based on the new recon gurable device architecture MPLD.... [more] |
RECONF2011-23 pp.7-12 |
| RECONF | 2010-09-16 16:10 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | An SA-based Placement and Routing Method Considering Cell Congestion for MPLDs Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN) RECONF2010-26 |
[more] | RECONF2010-26 pp.49-54 |
| RECONF | 2010-09-16 16:35 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Design and Implementation of a Layout Tool for the MPLD Architecture Ken Taomoto, Hideyuki Kawabata, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura (Hiroshima City Univ.) RECONF2010-27 |
A rapidly and partially reconfigurable fine-grain programmable logic device, named MPLD, has been proposed. The MPLD arc... [more] | RECONF2010-27 pp.55-60 |
| RECONF | 2009-09-18 13:10 |
Tochigi | Utsunomiya Univ. | High-density Implementation for Reconfigurable Device MPLD Hiroaki Toguchi, Masanori Asaeda, Yutaro Oda, Naoki Hirakawa, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN CO.LTD) RECONF2009-35 |
In recent years, a lot of Programmable Logic Device (PLD) such as Field Programmable Gate Array (FPGA) has been used. As... [more] | RECONF2009-35 pp.97-102 |
| CPSY | 2008-10-31 11:15 |
Hiroshima | Hiroshima City Univ. | [Special Invited Talk]
The Proposal of the MPLD Architecture for High Performance Computing Tetsuo Hironaka, Naoki Hirakawa (Hiroshima City Univ.), Masanori Yoshihara (Hiroshima City Univ./Renesas Technorogy Corp.), Kazuya Tanigawa (Hiroshima City Univ.), Masayuki Sato (Taiyo Yuden Co., Ltd.) CPSY2008-31 |
As the practical use of high performance FPGA increases, research on using FPGAs in the field of HPC (High Performance C... [more] | CPSY2008-31 pp.13-18 |
| RECONF | 2008-09-26 13:50 |
Okayama | Okayama Univ. | Consideration of Combinational Circuit Mapping Method for Reconfigurable Device MPLD Yutaro Oda, Kazuya Tanigawa, Tetsuo Hironaka, Naoki Hirakawa, Hiroaki Toguchi (Hiroshima City Univ.), Masayuki Sato (Taiyo Yuden) RECONF2008-37 |
As a novel Field Programmable Gate Array(FPGA), MPLD has been proposed. The MPLD consists of MLUTs. which has functions ... [more] | RECONF2008-37 pp.87-92 |
| WIT | 2008-03-23 14:45 |
Fukuoka | Kitakyushu Science and Research Park | Proposal of a Weighted-SPEAK method for cochlear implant system and design of its evaluation simulator Masayuki Satou (Kumamoto PCT), Masato Ikiyama, Dan Nishikido, Hiroki Toyoshima, Tadashi Sakata, Yuichi Ueda (Kumamoto Univ.) WIT2007-105 |
A hybrid method, which have proposed as a speech processor for the cochlear implant, is a mixture type of a general-purp... [more] | WIT2007-105 pp.85-90 |
| RECONF | 2007-09-20 13:30 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Implementation of Memory (MPLD) with The Ability to work as a Reconfigurable Device Masanori Yoshihara, Naoki Hirakawa, Kazuya Tanigawa, Tetsuo Hironaka (HCU), Masayuki Sato (GTI) RECONF2007-16 |
In recent years, FPGAs have been used as a reconfigurable device.As a problem of FPGAs, we cannot use FPGAs as one large... [more] | RECONF2007-16 pp.7-12 |
| R | 2007-09-14 14:05 |
Kochi | Kochi Univ. of Technology | Evaluation of transmission line for LSI tester and simulation modeling Hidekazu Tsuchiya, Takeshi Asakawa (Tokai univ.), Masayuki Sato (Genesis technology) R2007-34 |
Recently, the operating speed of LSI is more fast. Therefore, it is more important to evaluate the transmission line of ... [more] | R2007-34 pp.29-34 |
| RECONF | 2006-09-14 14:45 |
Kumamoto | Kumamoto Univ. | A logic design technique using SRAM blocks Masayuki Sato, Hiroki Wakamatsu (Ｇｔｉ) |
A low power on-board reconfigurable tester have been developed by using an FPGA. It is technically possible to configure... [more] | RECONF2006-23 pp.17-22 |
| RECONF | 2006-09-14 15:15 |
Kumamoto | Kumamoto Univ. | Discussion of Memory-LSI Working as Reconfigurable Device Masanori Yoshihara, Tetsuo Hironaka (HCU), Masayuki Sato (GTI) |
Each function included in SoC are usually tested by the built in test circuits in the chip.Testing the SoC by the built ... [more] | RECONF2006-24 pp.23-28 |
[Return to Top Page]