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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Scan-Out Power Reduction Method for Multi-Cycle BIST Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech)  VLD2012-102 DC2012-68 |
Excessive power dissipation in logic BIST is a serious problem. Although many low power BIST approaches that focus on sc... [more] | VLD2012-102 DC2012-68 pp.249-254 |
| DC | 2012-06-22 15:45 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | An Evaluation of Low Power BIST Method Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara (Kyutech) DC2012-14 |
Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophi... [more] | DC2012-14 pp.33-38 |
| DC | 2012-06-22 16:35 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | Evaluation of the on-chip temperature and voltage using ring-oscillator-based monitoring circuit and a study for an application to field test Yousuke Miyake, Takuma Sasakawa, Yasuo Sato, Seiji Kajihara (Kyutech), Yukiya Miura (TMU) DC2012-16 |
Delay increase due to aging phenomena is a critical issue of VLSIs. For detecting such increase in field, highly accurat... [more] | DC2012-16 pp.45-50 |
| DC | 2012-02-13 11:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A method to reduce shift-toggle rate for low power BIST Takaaki Kato, Senling Wang, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) DC2011-80 |
Logic BIST using scan design has a problem with high power dissipation during test. In this work we propose a method tha... [more] | DC2011-80 pp.25-29 |
| DC | 2012-02-13 16:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Evaluation of a thermal and voltage estimation circuit for field test Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech), Yukiya Miura (TMU) DC2011-86 |
High dependability is required for an embedded system VLSI. High functionality and high performance of VLSI, due to the ... [more] | DC2011-86 pp.61-66 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:05 |
Miyazaki | NewWelCity Miyazaki | Capture power reduction in multi-cycle test structure Hisato Yamaguchi, Makoto Matsuzono, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) VLD2011-83 DC2011-59 |
Power consumption during Built-In Self-Test(BIST) is far larger than that of normal operation. Therefore, it may lead to... [more] | VLD2011-83 DC2011-59 pp.179-183 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 15:25 |
Fukuoka | Kyushu University | Evaluation of Multi-Cycle Test with Partial Observation in Scan BIST Structure Hisato Yamaguchi, Makoto Matsuzono, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech./JST) VLD2010-61 DC2010-28 |
Reducing test data volume is important for field BIST because the data should be stored on a chip. In this paper, for th... [more] | VLD2010-61 DC2010-28 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 16:05 |
Fukuoka | Kyushu University | Rotating Test and Pattern Partitioning for Field Test Senling Wang, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Insti. Tech.) |
[more] | |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | [Invited Talk]
Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.) |
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are takin... [more] | |
| DC | 2010-02-15 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | On Calculation of Delay Test Quality for Test Cubes and X-filling Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech./JTS) DC2009-73 |
This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns... [more] | DC2009-73 pp.51-56 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 14:25 |
Kochi | Kochi City Culture-Plaza | A Path Selection Method of Delay Test for Transistor Aging Mitsumasa Noda (Kyushu Institute of Tech.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Institute of Tech./JST), Yukiya Miura (Tokyo Metropolitan Univ./JST) VLD2009-65 DC2009-52 |
With the advanced VLSI process technology, it is important for reliability of VLSIs to deal with faults caused by aging.... [more] | VLD2009-65 DC2009-52 pp.167-172 |
| DC | 2008-06-20 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg | [Invited Talk]
The State of the Art and Future Trends of Test Design Yasuo Sato (Hitachi) DC2008-15 |
As the manufacturing process evolves with shrinking geometry and the speed of an LSI circuit increases, LSI testing tech... [more] | DC2008-15 pp.23-28 |
| DC | 2008-06-20 16:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Transistor Aging and Operational Environment of Logic Circuits Masafumi Haraguchi (Kyushu Inst. of Tech.), Yukiya Miura (Tokyo Metropolitan Univ.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.) DC2008-17 |
With the progress of integrated circuit technology, it is becoming important to consider circuit aging. In this work we ... [more] | DC2008-17 pp.35-40 |
| R | 2007-09-14 13:10 |
Kochi | Kochi Univ. of Technology | [Invited Talk]
The Latest Trend of Defect Modeling in LSI Diagnosis
-- Tutorial -- Yasuo Sato (Hitachi) R2007-32 |
This paper addresses the latest trend of defect modeling for LSI diagnosis. Diagnosis methodology finds the suspicious n... [more] | R2007-32 pp.17-22 |
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