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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2014-04-18 11:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit Keiichi Kushida, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Azuma Suzuki, Yusuke Niki, Miyako Shizuno, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba)  ICD2014-13 |
This paper presents a dual-power-supply SRAM that reduces active and stand-by power from room temperature (RT) to high t... [more] | ICD2014-13 pp.65-70 |
| ICD | 2013-04-12 13:30 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Talk]
A Sense-Amplifier-Timing-Generating Circuit Utilizing a Statistical Method for Ultra Low Voltage SRAMs Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe (Toshiba) ICD2013-18 |
A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monit... [more] | ICD2013-18 pp.91-96 |
| ICD | 2013-04-12 14:20 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
A Power-Reduction Scheme for Dual-Power-Supply SRAM Using BL Power Calculator and Digital LDO Miyako Shizuno, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba) ICD2013-19 |
This paper presents a dual-power-supply SRAM that reduces active and stand-by power from room temperature (RT) to high t... [more] | ICD2013-19 pp.97-102 |
| ICD | 2011-04-19 09:55 |
Hyogo | Kobe University Takigawa Memorial Hall | A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe (Toshiba) ICD2011-9 |
A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static ... [more] | ICD2011-9 pp.49-54 |
| ICD | 2010-04-22 09:00 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
A Configurable SRAM with Constant-Negative-Level Write Buffer for Low Voltage Operation with 0.149μm2 Cell in 32nm High-k Metal Gate CMOS Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe (Toshiba Corp.) ICD2010-1 |
This paper presents a configurable SRAM for low voltage operation with Constant-Negative-Level Write Buffer (CNL-WB) and... [more] | ICD2010-1 pp.1-6 |
| SIP, ICD, IE, IPSJ-SLDM (Joint) [detail] |
2007-10-25 11:50 |
Fukushima | Aidu-Higasiyama-Onsen Kuturogijuku | An Analog Moving-Object-Localization VLSI System Employing OR-Amplification of Pixel Activities Yusuke Niki, Yasuo Manzawa, Satoshi Kametani, Tadashi Shibata (Univ. of Tokyo) SIP2007-114 ICD2007-103 IE2007-73 |
An analog VLSI for real-time moving object localization has been developed based on binarized pixel data (activity bits)... [more] | SIP2007-114 ICD2007-103 IE2007-73 pp.23-28 |
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