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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 10:15 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) |  CPSY2018-120 DC2018-102 |
We propose a MPU architecture for PLCs (Programmable Logic Controllers) and its complier. The ideaof the speed-up method... [more] | CPSY2018-120 DC2018-102 pp.333-339 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 10:35 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | CPSY2018-121 DC2018-103 |
We propose a speed-up method for PLCs (Programmable Logic Controllers) by only modifying program codes. Ladder diagram ... [more] |
CPSY2018-121 DC2018-103 pp.341-346 |
| SIS | 2009-03-05 15:45 |
Tokyo | [Special Talk]
System Realizations by Using Embedded Memories in FPGAs Yukihiro Iguchi (Meiji Univ.) |
FPGAs (Field Programmable Gate Arrays) have many embedded RAMs. We can use them for register files, FIFO (First In, Fi... [more] |
SIS2008-80 pp.49-54 |
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| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 11:20 |
Fukuoka | Kitakyushu International Conference Center | Design Methods for Radix Converters (4)
-- RNS to Binary Conversion -- Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao (Kyutech) RECONF2007-48 |
[more] | RECONF2007-48 pp.31-36 |
| ICD, VLD | 2007-03-08 15:30 |
Okinawa | Mielparque Okinawa | Design Method of Radix Converters Using Arithmetic Decompositions (3) Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT), Toshikazu Aoyama (Meiji Univ.) |
In digital signal processing, radixes other than two are often used for high-speed computation. In the computation f... [more] |
VLD2006-135 ICD2006-226 pp.97-102 |
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-30 10:55 |
Fukuoka | Kitakyushu International Conference Center | Design of Radix Converters Using Arithmetic Decomposition (2) Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) |
[more] | RECONF2006-47 pp.19-24 |
| RECONF | 2005-09-15 13:00 |
Hiroshima | On LUT cascade realizations of FIR filters using arithmetic decomposition Tsutomu Sasao (Kyutech), Yukihiro Iguchi, Takahiro Suzuki (Meiji Univ.) |
This paper first defines the n-input q-output WS function, as a mathematical model of the combinational part of the dist... [more] | RECONF2005-33 pp.19-24 |
|
| VLD, ICD | 2005-03-10 - 2005-03-11 |
Okinawa | Mielparque Okinawa | Hardware to Compute Walsh Coefficients Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao (Kyushu Institute of Technology) |
[more] | VLD2004-127 ICD2004-223 pp.17-22 |
| VLD, ICD | 2005-03-10 - 2005-03-11 |
Okinawa | Mielparque Okinawa | LUT Cascade Realization of FIR Filter Tsutomu Sasao (Kyushu Institute of Technology), Yukihiro Iguchi, Takahiro Suzuki (Meiji Univ.) |
[more] | VLD2004-126 ICD2004-222 pp.11-16 |
| CPSY, VLD, IPSJ-SLDM | 2005-01-26 16:50 |
Kanagawa | A Design of AES Encryption Circuit with 128-bit keys Using Look-Up Table Ring Hui Qin, Tsutomu Sasao (Kyushu Inst. of Tech.), Yukihiro Iguchi (Meiji Univ.) |
This paper presents a new architecture for the AES encryption. The key technique is the PPR architecture, which is suita... [more] | VLD2004-122 CPSY2004-88 pp.73-78 |
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