| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2008-12-12 13:25 |
Yamaguchi | A Test Generation Model for Threshold Testing Kenta Sutoh, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)  DC2008-60 |
Threshold testing, which is an LSI testing method based on the acceptability of faults, is effective in yield enhancemen... [more] | DC2008-60 pp.5-10 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:30 |
Fukuoka | Kitakyushu Science and Research Park | [Poster Presentation]
A Test Point Insertion Method for Test Data Reduction Based on Necessary Assignment Kazuko Hiramoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ) VLD2008-80 DC2008-48 |
In this work, we discuss a method for reducing test data by test point insertion. Focusing on the fact that test points ... [more] | VLD2008-80 DC2008-48 pp.121-126 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:55 |
Fukuoka | Kitakyushu Science and Research Park | [Poster Presentation]
A Hybrid Delay Scan forDelay Testing Based on Propagation Dominance Tomomi Nuwa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2008-81 DC2008-49 |
The hybrid delay scan design [1], where part of FFs can be controlled as skewed-load ones, is an effective method for a... [more] |
VLD2008-81 DC2008-49 pp.127-132 |
| DC, CPSY | 2008-04-23 11:30 |
Tokyo | Tokyo Univ. | A Study on Reliability and Performance of FPGA-Based Fault Tolerant Systems Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) CPSY2008-4 DC2008-4 |
FPGAs (Field-Programmable Gate Arrays), which can implement arbitrary logic circuits any number of times by loading con... [more] |
CPSY2008-4 DC2008-4 pp.19-24 |
| DC | 2008-02-08 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Synthesis of Fault Secure Datapaths with DFG Restructuring Hirotaka Shiomichi (Hiroshima City Univ.), Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City) DC2007-75 |
This paper considers a method for synthesizing fault secure datapaths by concurrent error detection. Defining the comp... [more] |
DC2007-75 pp.51-56 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:55 |
Fukuoka | Kitakyushu International Conference Center | An optimization of thru trees for test generation based on acyclical testability Kohsuke Morinaga, Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2007-72 DC2007-27 |
The class of acyclic sequential circuits is $\tau^2$-bounded, i.e., acyclic sequential circuits are practically easily t... [more] | VLD2007-72 DC2007-27 pp.13-18 |
| CPSY, DC | 2007-04-20 14:15 |
Tokyo | A scheduling algorithm in high-level synthesis for soft error tolerance with chained operations Shintaro Imamura, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) CPSY2007-2 DC2007-2 |
Soft errors refer to intermittent malfunctions, which are not physical defects. Due to the high speed and low voltage o... [more] |
CPSY2007-2 DC2007-2 pp.7-12 |
|
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-28 10:55 |
Fukuoka | Kitakyushu International Conference Center | A Method of Test Plan Generation in Hierarchical Test Based on Balanced Structure Yudai Kawahara, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
[more] | VLD2006-55 DC2006-42 pp.23-28 |
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-28 11:20 |
Fukuoka | Kitakyushu International Conference Center | Test Compression/Decompression with the Decoding Function in Multimedia Cores Yukinori Setohara, Yusuke Nakashima, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
[more] | VLD2006-56 DC2006-43 pp.29-34 |
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-28 16:35 |
Fukuoka | Kitakyushu International Conference Center | A Self-Test of Dynamically Reconfigurable Processors Takashi Fujii, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
Dynamically Reconfigurable Processor (DRP), which can execute a task with multiple hardware contexts so as to achieve hi... [more] | VLD2006-62 DC2006-49 pp.65-70 |
| RECONF | 2005-05-12 09:30 |
Kyoto | Kyoto University | A Reconfigurable Embedded Decompressor for LSI Testing Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
The problem of the increase in test data size for large-scale curcuits has developed. In order to solve this problem, s... [more] |
RECONF2005-1 pp.1-6 |
| ICD, CPM | 2005-01-28 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A decompressor with buffer for test compression / decompression Michihiro, Masakuni Ochi, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
Test compression / decompression scheme using variable-length coding, e.g., Huffman coding, is effective in reducing the... [more] | CPM2004-168 ICD2004-213 pp.35-40 |
| NLP | 2005-01-24 17:30 |
Kagawa | Kagawa Univ. | * Kenichi Yukumatsu, Suguru Matsumoto, Yoshinori Matsuura, Tomoo Inoue (Hiroshima City Univ.) |
[more] | NLP2004-98 pp.51-56 |
[Return to Top Page]