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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2013-02-13 10:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Hardware Implementation of a SAT Solver for Test Generation with Solution Reuse Toshiya Mukai, Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)  DC2012-80 |
[more] | DC2012-80 pp.1-6 |
| DC | 2013-02-13 15:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Method of Acceptable Fault Identification with Necessary Assignment in Logic Simplification for Error Tolerant Application Shingo Matsuki, Junpei Kamei, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2012-88 |
In error tolerant applications, some specific errors, which are of certain types or have severities within certain limit... [more] | DC2012-88 pp.49-54 |
| DC | 2012-12-14 16:00 |
Fukui | Aossa (Fukui) | A Test Generation Model for Over-testing Alleviation and Its Application to Testing Based on Fault Acceptability Masaaki Sakurada, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (HCU) DC2012-77 |
Over-testing, which is to judge fault-free chips as faulty ones, is a cause of the decrease in the effective yield of ch... [more] | DC2012-77 pp.21-26 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Effective Orderings of Instances and Variable Assignments in SAT-based ATPG with Solution Reuse Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2012-83 DC2012-49 |
This report discusses the efficiency of iteratively solving various instances with solution reuse in test generation ba... [more] |
VLD2012-83 DC2012-49 pp.141-146 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Heuristic Algorithm for Operational Unit Binding in Transient Fault Tolerant Datapath Synthesis Tatsuya Nakaso, Ryoko Ohkubo, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2012-84 DC2012-50 |
Due to the increase in the integration, operational speed and application complexity, the tolerance for transient faul... [more] |
VLD2012-84 DC2012-50 pp.147-152 |
| DC | 2012-06-22 13:50 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | A Study on Fault Tolerant Test Pattern Generators for Reliable Built-in Self Test Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2012-11 |
In the BIST (built-in self-test) scheme, the occurrence of faults in BIST circuits, such as TPGs (test pattern generator... [more] | DC2012-11 pp.15-20 |
| VLD | 2012-03-06 15:55 |
Oita | B-con Plaza | Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools Takehiro Mikami, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2011-130 |
A circuit has many false paths on which signal transitions never affect its circuit behavior.This report proposes a logi... [more] | VLD2011-130 pp.61-66 |
| VLD | 2012-03-07 15:40 |
Oita | B-con Plaza | A Design of Low-Power Color Interporation Circuits Based on Color Difference Kouta Omobayashi, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2011-143 |
Color interpolation, reproducing the original colors from restricted color information of a given image, is an im- porta... [more] | VLD2011-143 pp.139-144 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 09:00 |
Miyazaki | NewWelCity Miyazaki | Modeling Economics of LSI Design and Manufacturing for Selecting Test Design. Noboru Shimizu, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2011-71 DC2011-47 |
Many test designs (or DFTs: designs-for-testability) have been proposed to overcome some issues around LSI testing. In... [more] |
VLD2011-71 DC2011-47 pp.115-120 |
| DC | 2011-06-24 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Effective multi-cycle signatures in testable response analyzers Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2011-9 |
In the BIST (built-in self-test) scheme, we have proposed a concurrent testable response analyzer, called an encoding-ba... [more] | DC2011-9 pp.5-10 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 14:50 |
Fukuoka | Kyushu University | A Binding Algorithm for Multi-cycle Fault Tolerant Datapaths Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2010-60 DC2010-27 |
As the advance in semiconductor technology, the issue of soft errors, which are transient glitches caused by particle st... [more] | VLD2010-60 DC2010-27 pp.25-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 16:25 |
Fukuoka | Kyushu University | Experimental Evaluation of Built-in Test Pattern Generation with Image Decoders Yuka Iwamoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2010-63 DC2010-30 |
Built-in Self Test (BIST) is one of effective methods for testing today's very large-scale SoCs.In BIST scheme, a t... [more] | VLD2010-63 DC2010-30 pp.43-48 |
| DC | 2010-06-25 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Class of Partial Thru Testable Sequential Circuits with Multiplexers Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2010-9 |
Partially thru testable sequential circuits are known to be practically testable, and a condition for the testable seque... [more] | DC2010-9 pp.7-11 |
| DC | 2010-06-25 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Binding Algorithm in High-Level Synthesis for Robust Testable Datapaths Yuki Yoshikawa, Shun Maruya, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2010-10 |
[more] | DC2010-10 pp.13-18 |
| DC | 2010-02-15 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Acceptable Faults in Digital Filters Takumi Miyaguchi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2009-75 |
In this paper, we propose a method for distinguishing acceptable and unacceptable faults in digital filters. Analyzing t... [more] | DC2009-75 pp.63-68 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-27 14:05 |
Kanagawa | Keio Univ (Hiyoshi Campus) | An Implementation of Fail-soft Systems with Adaptive Fault Tolerance using SRAM-based FPGAs Satoshi Fujie, Ryoji Noji, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2009-93 CPSY2009-75 RECONF2009-78 |
Fail-soft systems with reconfigurable devices, which recover themselves by repeating isolation of faulty portions with g... [more] | VLD2009-93 CPSY2009-75 RECONF2009-78 pp.149-154 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 13:45 |
Kochi | Kochi City Culture-Plaza | A Yield Model with Testability and Repairability Yujiro Amano, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2009-54 DC2009-41 |
For deep-submicron technology, the increase in transitive and permanent faults of LSIs is a critical problem due to the ... [more] | VLD2009-54 DC2009-41 pp.89-94 |
| DC | 2009-06-19 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Algorithm Based on 5-valued Logic for Threshold Testing Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2009-12 |
If the existence of a fault in a circuit only causes negligible effect on its application, the fault is said to be acce... [more] |
DC2009-12 pp.13-18 |
| DC, CPSY | 2009-04-21 15:45 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | A design of testable response analyzers in built-in self-test Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) CPSY2009-7 DC2009-7 |
In the BIST(Built-in self-test) scheme, the occurrence of faults in BIST circuits, e.g., test generators and response co... [more] | CPSY2009-7 DC2009-7 pp.37-42 |
| DC | 2009-02-16 10:00 |
Tokyo | On the Acceleration of Threshold Test Generation Based on Fault Acceptability Yusuke Nakashima, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ) DC2008-68 |
[more] | DC2008-68 pp.1-6 |
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