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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 09:00 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Overview of an HLS Framework Surpporting IoT/CPS Development Daichi Teruya, Hironori Nakajo (TUAT)  VLD2016-80 CPSY2016-116 RECONF2016-61 |
[more] | VLD2016-80 CPSY2016-116 RECONF2016-61 pp.61-66 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 09:25 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Framework for a Hybrid System with a pair of MCU and FPGA Ryota Suzuki, Nakajo Hironori (TUAT) VLD2016-81 CPSY2016-117 RECONF2016-62 |
Recently, FPGAs for mobile use which have low pin count and small packages are commonly available. Due to limitation of... [more] |
VLD2016-81 CPSY2016-117 RECONF2016-62 pp.67-72 |
| RECONF | 2016-05-19 14:15 |
Kanagawa | FUJITSU LAB. | Efficiency Execution of Split Circuit in a Scalable Hardware System by Signal Compression Yoshio Murata, Hironari Yoshiuchi, Hironori Nakajo (TUAT) RECONF2016-8 |
(To be available after the conference date) [more] | RECONF2016-8 pp.35-40 |
| RECONF | 2016-05-20 10:45 |
Kanagawa | FUJITSU LAB. | A Sound Field Visualizer with Java-based High Level Synthesis Tool and CoRAM Architecture Synthesis Framework Daichi Teruya, Daichi Miyazaki, Hironori Nakajo (TUAT) RECONF2016-20 |
Currently the number of devices which uses multiple sensors has been increasing due to recent significant interest on th... [more] | RECONF2016-20 pp.97-102 |
| RECONF | 2015-09-18 14:55 |
Ehime | Ehime University | Overview of the Reconfigurable Virtual Accelerator ReVA Hironori Nakajo, Yuki Oigo (TUAT), Shozo Takeoka (AXE), Masashi Takemoto (BeatCraft), Takefumi Miyoshi (Wasalabo) RECONF2015-40 |
[more] | RECONF2015-40 pp.45-50 |
| PRMU, CNR | 2015-02-20 16:30 |
Miyagi | Smart space for unconstrained monitoring of office activity
-- Automatic estimation of communication and task activities -- Kinya Fujita, Masano Nakayama, Hiroaki Murata, Hitomi Yokoyama, Seiji Hotta, Ikuko Shimizu, Takafumi Saito, Toshiyuki Kondo, Hironori Nakajo, Kaori Fujinami, Katsuhide Fujita (TUAT) PRMU2014-155 CNR2014-70 |
For long-term automatic analysis of office activities, an intelligent environment is desired, which enables unconstraine... [more] | PRMU2014-155 CNR2014-70 pp.215-220 |
|
| CPSY, DC (Joint) |
2014-07-29 09:00 |
Niigata | Toki Messe, Niigata | Verification Method of the Split Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism Kazuya Matsuda (TAT), Takefumi Miyoshi (e-trees.Japan), Masashi Takemoto (TAT), Satoshi Funada (e-trees.Japan), Hironori Nakajo (TAT) CPSY2014-17 |
In recent years, a high-level synthesis tool has been attracted in designing hardware circuits instead of traditional HD... [more] | CPSY2014-17 pp.43-48 |
| RECONF | 2014-06-12 15:35 |
Miyagi | Katahira Sakura Hall | Implementation of a RISC Processor with a Complex Instruction Accelerator
-- Return to a CISC -- Ryota Suzuki (Tokyo Univ. of Agriculture and Tech.), Takefumi Miyoshi (e-trees), Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) RECONF2014-13 |
In this paper, we propose a RISC processor with an accelerator which can execute a complex instruction with a co-proces... [more] |
RECONF2014-13 pp.67-72 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 10:25 |
Kanagawa | Hiyoshi Campus, Keio University | A Storing and Regenerating Signal Information in a Scalable Hardware System Yusuke Katoh, Daisuke Watanabe, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech) VLD2013-106 CPSY2013-77 RECONF2013-60 |
In implementing a large-scale circuit into a single LSI, limitation of circuit area or degradation of maximum operating ... [more] | VLD2013-106 CPSY2013-77 RECONF2013-60 pp.25-30 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 10:50 |
Kanagawa | Hiyoshi Campus, Keio University | Hardware Expansion Protocol in a Scalable Hardware System Daisuke Watanabe, Yusuke Katoh, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) VLD2013-107 CPSY2013-78 RECONF2013-61 |
Recently hardware acceleration with using an FPGA are focused as well as prototyping an ASIC with it. The available numb... [more] | VLD2013-107 CPSY2013-78 RECONF2013-61 pp.31-36 |
| HCGSYMPO (2nd) |
2013-12-18 - 2013-12-20 |
Ehime | Matsuyama Multi-Purpose Community Cente | Environmental sensing system for grasp and prediction of a group behavior
-- Speaker localization using directional microphones -- Hiroaki Murata, Masano Nakayama, Katsuhide Fujita, Ikuko Shimizu, Seiji Hotta, Kaori Fujinami, Toshiyuki Kondo, Hironori Nakajo, Takafumi Saito, Kinya Fujita (Tokyo Univ. of Agr. and Tech.) |
We are developing “Smart Space Technology toward Sustainable Society” which is the environmental sensing system for gras... [more] | |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-27 10:50 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Hardware Acceleration in a Scalable FPGA System Hironori Nakajo, Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.) VLD2009-88 CPSY2009-70 RECONF2009-73 |
Currently, FPGAs are utilized for hardware experiments or practices in many educational institutes. In a field of high ... [more] |
VLD2009-88 CPSY2009-70 RECONF2009-73 pp.119-124 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-27 11:15 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Expansion of Hardware in a Scalable FPGA System Hironori Nakajo (Tokyo Univ. of Agr and Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech.), Satoshi Funada (e-trees.Japan, Inc), Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.) VLD2009-89 CPSY2009-71 RECONF2009-74 |
Currently, in a field of high performance computing, some FPGAs are utilized to accelerate processing against some forma... [more] | VLD2009-89 CPSY2009-71 RECONF2009-74 pp.125-130 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 14:45 |
Kochi | Kochi City Culture-Plaza | Protocol for Expansion of Hardware in a Scalable FPGA System Hironori Nakajo, Ryuichi Sakamoto, Shinobu Miwa (TUAT) |
In this presentation, we have proposed a mechanism to expand hardware in the Scalable FPGA system which has been current... [more] | |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 13:15 |
Osaka | Shoushin Kaikan | Feasibility of an Embedded Virtual Machine under Parallel or Distributed Processing Environment Hirofumi Yano, Masaki Nakanishi, Shinobu Miwa, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) |
[more] | ICD2008-142 pp.75-80 |
| RECONF | 2005-05-12 11:00 |
Kyoto | Kyoto University | Implementation of an SMT Processor and its Reconfigurable Cache with FPGA Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo (Tokyo University of Agriculture and Technology) |
Recently, it becomes possible to implement a large-scale processor due to speed-up and large-scale integrity of an FPG... [more] |
RECONF2005-4 pp.19-24 |
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