Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD, SDM, ITE-IST [detail] |
2016-08-03 09:00 |
Osaka |
Central Electric Club |
[Invited Talk]
SRAM PUF using Polycrystalline Silicon Channel FinFET and Its Evaluation Shin-ichi O'uchi, Yungxun Liu, Yohei Hori, Toshifumi Irisawa, Hiroshi Fuketa, Yukinori Morita, Shinji Migita, Takahiro Mori, Tadashi Nakagawa, Junichi Tsukada, Hanpei Koike, Meishoku Masahara, Takashi Matsukawa (AIST) SDM2016-60 ICD2016-28 |
[more] |
SDM2016-60 ICD2016-28 pp.83-87 |
RECONF |
2015-06-20 14:00 |
Kyoto |
Kyoto University |
On the Evaluation Board AISTino equipped with the Fourth Flex Power FPGA chip with SOTB transistors Hanpei Koike, Masakazu Hioki, Yasuhiro Ogasahara (AIST), Hayato Ishigaki, Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa (AIST) RECONF2015-22 |
Flex Power FPGA utilizes threshold voltage programmability to reduce its static power by the body bias control of circui... [more] |
RECONF2015-22 pp.119-124 |
RECONF |
2014-09-18 17:20 |
Hiroshima |
|
On The Second Flex Power FPGA Chip with SOTB Transistors Hanpei Koike (AIST), Chao Ma (Meiji Univ.), Masakazu Hioki, Yasuhiro Ogasahara (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa (AIST) RECONF2014-24 |
[more] |
RECONF2014-24 pp.41-46 |
RECONF |
2014-06-12 10:25 |
Miyagi |
Katahira Sakura Hall |
Improvement of Implementability by Exploring Routing Architecture in Flex Power FPGA Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Yasuhiro Ogasahara (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Hanpei Koike (AIST) RECONF2014-5 |
(To be available after the conference date) [more] |
RECONF2014-5 pp.21-25 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 13:45 |
Kagoshima |
|
Evaluation of The First Flex Power FPGA chip with SOTB transistors Chao Ma (AIST/Meiji Univ.), Masakazu Hioki (AIST), Takashi Kawanami (KIT), Yasuhiro Ogasahara, Tadashi Nakagawa, Toshihiro Sekigawa (AIST), Toshiyuki Tsutsumi (AIST/Meiji Univ.), Hanpei Koike (AIST) RECONF2013-53 |
Flex Power FPGA was able to utilize a programmable threshold voltage to each circuit block of the FPGA by using the body... [more] |
RECONF2013-53 pp.77-82 |
ICD, ITE-IST |
2013-07-05 16:50 |
Hokkaido |
San Refre Hakodate |
A Study on 1/f Noise Characteristic in Independent-Double-Gate-FinFET Hideo Sakai (Keio Univ.), Shin-ichi O'uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Yuki Ishikawa, Junichi Tsukada, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Meishoku Masahara (AIST), Hiroki Ishikuro (Keio Univ.) ICD2013-43 |
In this work, we measured 1/f noise of Independent-Double-Gate- (IDG-) FinFET which has two independent gates. Flicker n... [more] |
ICD2013-43 pp.119-124 |
RECONF |
2012-05-29 11:00 |
Okinawa |
Tiruru (Naha Okinawa, Japan) |
Development of a demonstration system for Ultra-low-power FPGA with Fine-Grained Field-Programmable Threshold Voltage Control Takashi Kawanami (KIT), Masakazu Hioki (AIST), Yohei Matsumoto (Kaiyo Univ.), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) RECONF2012-5 |
The Flex Power FPGA is a new FPGA architecture which enabled high speed operation and low power-consumption by fine-grai... [more] |
RECONF2012-5 pp.25-30 |
ICD |
2011-04-19 10:55 |
Hyogo |
Kobe University Takigawa Memorial Hall |
0.5-V FinFET SRAM Using Dynamic-Threshold-Voltage Pass Gates Shin-ichi O'uchi, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara (AIST) ICD2011-11 |
This article presents a FinFET SRAM which salvages malfunctioned bits caused by random variation. In the presenting SRAM... [more] |
ICD2011-11 pp.59-63 |
SDM, ED |
2011-02-23 16:30 |
Hokkaido |
Hokkaido Univ. |
A Study on Precise FinFET High Frequency Characteristic Evaluation Method Hideo Sakai (Keio Univ.), Shinichi Ouchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara (AIST), Hiroki Ishikuro (Keio Univ.) ED2010-198 SDM2010-233 |
In recent years, different research groups have been focusing on FinFET transistor research as an excellent replacement ... [more] |
ED2010-198 SDM2010-233 pp.37-42 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 09:50 |
Fukuoka |
Kyushu University |
Fabrication in Low Power Process and Evaluation of Power Reconfigurable Field Programmable Gate Array Masakazu Hioki (AIST), Takashi Kawanami (KIT), Yohei Matsumoto (TUMSAT), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) RECONF2010-45 |
Flex Power FPGA that is FPGA with power reconfigurability aims at the reduction of static power. The reduction of off cu... [more] |
RECONF2010-45 pp.37-42 |
RECONF |
2009-09-17 15:40 |
Tochigi |
Utsunomiya Univ. |
Design and Fabrication of Flex Power FPGA with Power Reconfigurability Masakazu Hioki (AIST), Takashi Kawanami (Kanazawa Inst. of Tech.), Yohei Matsumoto (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) RECONF2009-25 |
Our research group has evaluated “Flex Power FPGA” which can reconfigure the power from the viewpoint of software and ha... [more] |
RECONF2009-25 pp.37-42 |
RECONF |
2006-09-14 15:45 |
Kumamoto |
Kumamoto Univ. |
Yield enhancement of FPGAs with intra-die variation using multiple configuration data Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
[more] |
RECONF2006-25 pp.29-34 |
RECONF |
2006-05-18 14:15 |
Miyagi |
TOHOKU UNIVERSITY |
Detail Analysis of Optimal Body Bias Voltage Set for Flex Power FPGA Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
The Flex Power FPGA is a new FPGA architecture which enabled high speed operation and low power-consumption by controlli... [more] |
RECONF2006-4 pp.19-24 |
RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18 10:00 |
Kanagawa |
|
Optimization of Body Bias Voltage Set for Threshold Voltage Control in Flex Power FPGA Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
The Flex Power FPGA is a new FPGA architecture which enabled high speed operation and low power-consumption by controlli... [more] |
VLD2005-97 CPSY2005-53 RECONF2005-86 pp.1-6 |
RECONF |
2005-09-16 11:00 |
Hiroshima |
|
Evaluation of Vth Control Region Granularity in Flex Power FPGA Masakazu Hioki, Takashi Kawanami (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
Flex Power FPGA can flexibly control the operating speed and power consumption by the threshold voltage of transistor. T... [more] |
RECONF2005-45 pp.25-30 |
RECONF |
2005-09-16 11:30 |
Hiroshima |
|
Implementation of Optimal Vth Assigning Algorithm in Flex Power FPGA Takashi Kawanami, Masakazu Hioki (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
The Flex Power FPGA is a new FPGA architecture which enabled high speed and low power consumption by controling threshol... [more] |
RECONF2005-46 pp.31-36 |
RECONF |
2005-05-12 15:45 |
Kyoto |
Kyoto University |
Analyses of Operating Speed and Power Consumption in Flex Power FPGA
-- From Circuit Level To Chip Level -- Masakazu Hioki, Takashi Kawanami (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
Flex Power FPGA can flexibly control the operating speed and power consumption by the threshold voltage of transistor. T... [more] |
RECONF2005-10 pp.55-60 |
RECONF |
2005-05-12 16:15 |
Kyoto |
Kyoto University |
Area Overhead Estimation for Vth Control in Flex Power FPGA Takashi Kawanami, Masakazu Hioki (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
The Flex Power FPGA is a new FPGA architecture which enabled high speed and low power consumption by controling threshol... [more] |
RECONF2005-11 pp.61-66 |
|