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Paper #
SIP
,
ICD
,
IE
,
IPSJ-SLDM
2005-10-20
15:30
Miyagi
Ichinobo, Sakunami-Spa
A Memory Controller that Reduces Latency of Cached SDRAM
Seiji Miura
,
Satoru Akiyama
(
Hitachi,Ltd
)
The proposed controller has two main control schemes, address-alignment control and dummy-cache control scheme. These tw...
[more]
SIP2005-110
ICD2005-129
IE2005-74
pp.89-93
ICD
2004-12-16
10:30
Hiroshima
A Dynamic SDRAM-Mode Control Scheme for Low-Power Systems
Seiji Miura
,
Kazushige Ayukawa
(
Hitachi,Ltd
)
A dynamic SDRAM-mode-control scheme for low-power systems was developed and tested. The scheme is based on two dynamic c...
[more]
ICD2004-184
pp.7-11
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