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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-29
10:05
Kanagawa   Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array
Kazuki Sato, Baatarsuren Bars, Masatoshi Sekine (Tokyo Univ. of Agriculture and Tech.) VLD2008-94 CPSY2008-56 RECONF2008-58
In recent years, the examples which use FPGA for the HPC use are increasing. We propose FPGA array which accumulated a l... [more] VLD2008-94 CPSY2008-56 RECONF2008-58
pp.19-24
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