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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, ICD, ITE-IST [detail] | 2019-08-09 10:50 |
Hokkaido | Hokkaido Univ., Graduate School /Faculty of Information Science and | [Invited Talk]
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture supporting ISO26262 ASIL-D Naoto Okumura, Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Shohei Maeda, Tomonori Yanagita, Takao Koike, Masao Ito, Minoru Uemura, Yasuhisa Shimazaki, Toshihiro Hattori, Noriaki Sakamoto, Hiroyuki Kondo (Renesas Electronics Corp.)  SDM2019-47 ICD2019-12 |
Along with the rapid progress of automotive Electrical/Electronic(E/E) architecture, further integration of multiple ele... [more] | SDM2019-47 ICD2019-12 pp.67-71 |
| ICD, SDM | 2014-08-04 10:50 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | A 28nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor with 2GHz Cores and Low-Power 1GHz Cores Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori (Renesas Electronics) SDM2014-64 ICD2014-33 |
This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application pro... [more] | SDM2014-64 ICD2014-33 pp.11-16 |
| ICD | 2009-12-15 17:00 |
Shizuoka | Shizuoka University (Hamamatsu) | A 3D Processor Using Inductive-Coupling Inter-Chip Link
-- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM -- Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.) ICD2009-105 |
A 90nm CMOS processor is mounted face down on a package by C4 bump and a 65nm CMOS 1MB SRAM is glued on it face up. The ... [more] | ICD2009-105 pp.163-168 |
| ICD, IPSJ-ARC | 2008-05-13 10:30 |
Tokyo | An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.) |
In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which e... [more] | ICD2008-20 pp.19-24 |
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| ICD, IPSJ-ARC | 2007-05-31 13:45 |
Kanagawa | Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura (Waseda Univ.), Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Masaki Ito, Makoto Satoh, Kunio Uchiyama (Hitachi Ltd.) |
Currently, multicore processors are becoming ubiquitous in various computing domains, namely con- sumer electronics suc... [more] |
ICD2007-21 pp.25-30 |
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| ICD, IPSJ-ARC | 2007-05-31 14:15 |
Kanagawa | A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption Kiyoshi Hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa (Renesas technology), Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka (Hitachi Ltd.), Kiwamu Takada (Hitachi ULSI Systems Co. Ltd.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) ICD2007-22 |
4320MIPS 4-processor SoC that provides with low power consumption and high performance was designed using 90nm process. ... [more] | ICD2007-22 pp.31-35 |
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| ICD | 2006-05-25 13:30 |
Hyogo | Kobe University | Hierarchical Power Distribution with dozens of power domain in 90-nm Low-power SoCs Yusuke Kanno (HCRL), Hiroyuki Mizuno (Hitachi), Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi (Renesas), Toshifumi Ishii (Hitachi ULSI), Tetsuya Yamada (HCRL), Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa (Renesas), Naohiko Irie (HCRL) |
[more] | ICD2006-26 pp.25-30 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-21 10:10 |
Miyagi | Ichinobo, Sakunami-Spa | Development of an embedded processor core SH-X2 Takashi Okada (Hitachi), Tomoichi Hayashi, Takehiro Shimizu (Renesas), Fumio Arakawa, Tetsuya Yamada (Hitachi), Osamu Nishii, Toshihiro Hattori (Renesas) |
A {S}uper{H$^{\rm TM}$} embedded processor core, SH-X2 for consumer appliances, implemented in a 90-nm CMOS process runn... [more] | SIP2005-118 ICD2005-137 IE2005-82 pp.19-24 |
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