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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
An Autonomous Control Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory Yuta Kimi, Yohei Nakata, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa (Kobe Univ.), Makoto Nagata (Kobe Univ./JST CREST), Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai (Renesas Electronics Corporation), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST CREST)  ICD2013-125 |
Processor reliability is getting more critical issue since technology scaling degrades processor tolerance against power... [more] | ICD2013-125 p.59 |
| ICD | 2012-12-18 09:55 |
Tokyo | Tokyo Tech Front | A Stable Chip-ID Generating Physical Uncloneable Function Using Random Address Errors in SRAM Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii (Renesas) ICD2012-114 |
[more] | ICD2012-114 pp.91-95 |
| ICD | 2012-04-24 15:40 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | A Chip-ID Generating Circuit for Dependable LSI using Random Address Errors on Embedded SRAM and On-Chip Memory BIST Hidehiro Fujiwara, Makoto Yabuuchi, Hirofumi Nakano, Hiroyuki Kawai, Koji Nii, Kazutami Arimoto (Renesas Electronics) ICD2012-17 |
[more] | ICD2012-17 pp.91-95 |
| SDM, ICD | 2011-08-26 14:40 |
Toyama | Toyama kenminkaikan | Dependable SRAM with Enhanced Read-/Write-Margins by Fine-Grained Assist Bias Control for Low-Voltage Operation Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto (Renesas) SDM2011-91 ICD2011-59 |
[more] | SDM2011-91 ICD2011-59 pp.103-108 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 11:15 |
Osaka | Shoushin Kaikan | Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose core... [more] | ICD2008-140 pp.63-68 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 11:45 |
Osaka | Shoushin Kaikan | Local Memory Management Scheme by a Compiler for Multicore Processor Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
This paper proposes a local memory management scheme for an automatic parallelizing compiler to realize effective use o... [more] | ICD2008-141 pp.69-74 |
| VLD, ICD | 2008-03-07 14:40 |
Okinawa | TiRuRu | Implementation and Evaluation of Network Security using An Embedded Programmable Logic Matrix (ePLX) Mitsutaka Matsumoto, Shun Kimura (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology Corp.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) VLD2007-165 ICD2007-188 |
Low Cost Network Appliance with low power microprocessor must be connected with networks in order to realize ubiquitous ... [more] | VLD2007-165 ICD2007-188 pp.53-58 |
| EA, US (Joint) |
2008-01-29 11:00 |
Osaka | Kansai University | The study of sound source separation by two microphone system Hirofumi Nakano, Kensaku Fujii (Univ of Hyogo), Mitsuji Muneyasu (Kansai Univ) EA2007-104 |
We propose a novel microphone system characterized by two microphones. This system has two filters, one estimates an imp... [more] | EA2007-104 pp.19-24 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:10 |
Fukuoka | Kitakyushu International Conference Center | A Development of the Auto mapping tool for embedded Programmable Logic matriX (ePLX) and the study of ePLX local architecture Kouta Ishibashi, Yoshiyuki Tanaka, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Masaya Yoshikawa (Meijo Univ.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) RECONF2007-32 |
We propose a ePLX(embedded Programmable Logic matriX)which will be embedded in SoC.The ePLX consists of small area and a... [more] | RECONF2007-32 pp.1-6 |
| EA | 2007-11-16 11:30 |
Kumamoto | Kumamoto University | A study of speech separation using two microphone system Hirofumi Nakano, Kensaku Fujii (Univ of Hyogo), Mitsuji Muneyasu (Kansai Univ) EA2007-83 |
We alraedy proposed a microphone system characterized by using two filters.However,it has a severe problem which is inc... [more] | EA2007-83 pp.19-24 |
| ICD, IPSJ-ARC | 2007-05-31 13:45 |
Kanagawa | Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura (Waseda Univ.), Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Masaki Ito, Makoto Satoh, Kunio Uchiyama (Hitachi Ltd.) |
Currently, multicore processors are becoming ubiquitous in various computing domains, namely con- sumer electronics suc... [more] |
ICD2007-21 pp.25-30 |
|
| EA, US (Joint) |
2007-01-25 14:30 |
Kyoto | Doshisha Univ. | A Study on Noise Reduction Method Using Two Microphone System Hirofumi Nakano, Kensaku Fujii (Univ. Of Hyogo), Mitsuji Muneyasu (Kansai Univ.) |
[more] | EA2006-100 pp.15-20 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2007-01-18 13:25 |
Tokyo | Keio Univ. Hiyoshi Campus | Analysis of design architecture of ePLX ( embedded Programmable Logic matriX) and Evaluation of circuit mapping Tomoo Hishida, Kouta Ishibashi, Shun Kimura, Naoki Okuno, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) |
Recently, non-recurring engineering costs (NREs), including cost of mask-sets, and engineering design efforts are critic... [more] | VLD2006-100 CPSY2006-71 RECONF2006-71 pp.37-42 |
| EA, SIP | 2006-05-25 16:50 |
Hyogo | EGRET Himeji | noise reduction method by two microphone array system Hirofumi Nakano, Kensaku Fujii (Univ Of Hyogo), Yoshio Itoh (Tottori University) |
[more] | EA2006-14 SIP2006-18 pp.35-40 |
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