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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 8 of 8  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RCS, SR, SRW
(Joint)
2024-03-14
14:05
Tokyo The University of Tokyo (Hongo Campus), and online
(Primary: On-site, Secondary: Online)
[Invited Talk] Real-time cloud robotics and related technologies toward Beyond 5G/6G
Tomoya Tandai (TISS), Daisuke Uchida, Satoshi Takaya, Yuki Yonezawa (Toshiba), Hiroyuki Nishikawa (TISS), Daisuke Yamamoto (Toshiba) RCS2023-277 SR2023-100 SRW2023-64
This report proposes a Multi-access Edge Computing (MEC)-centralized mobile robots control and its related technologies ... [more] RCS2023-277 SR2023-100 SRW2023-64
p.126(RCS), p.58(SR), p.91(SRW)
SDM, ICD, ITE-IST [detail] 2023-08-03
13:45
Hokkaido Hokkaido Univ. Multimedia Education Bldg. 3F
(Primary: On-site, Secondary: Online)
[Invited Talk] Load Adaptive Active Gate Driver Integrated Circuit for Power Device
Shusuke Kawai, Takeshi Ueno, Satoshi Takaya, Koutaro Miyazaki (Toshiba), Kohei Onizuka (Toshiba Europe Limited), Hiroaki Ishihara (Toshiba) SDM2023-51 ICD2023-30
 [more] SDM2023-51 ICD2023-30
pp.64-69
MRIS, ITE-MMS 2018-07-06
16:35
Tokyo Waseda Univ. Ultra-high-efficient Writing in Voltage-Control Spintronics Memory(VoCSM)
Altansargai Buyandalai, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi, Yuichi Ohsawa, Naoharu Shimomura, Satoshi Shirotori, Hideyurki Sugiyama, Yushi Kato, Mizue Ishikawa, Katsuhiko Koi, Soichi Oikawa, Kazutaka Ikegami, Satoshi Takaya, Shinobu Fujita, Atsushi Kurobe (Toshiba Corporation)
 [more]
SDM 2016-01-28
15:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme
Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] SDM2015-126
pp.27-30
ICD, ITE-IST 2011-07-22
10:25
Hiroshima Hiroshima Institute of Technology Analysis Methods of Substrate Sensitivity in an Analog Circiut
Satoshi Takaya, Yoji Bando (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2011-28
Substrate noise sensitivity of an analog circuit consists of the sensitivity of a device and noise propagation from the ... [more] ICD2011-28
pp.73-78
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-29
11:20
Fukuoka Kyushu University A Consideration of Substrate Noise Sensitivity of Analog Elements
Satoshi Takaya, Yoji Bando, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) CPM2010-126 ICD2010-85
Measure substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 32 different geometor... [more] CPM2010-126 ICD2010-85
pp.13-17
ICD, ITE-IST 2010-07-22
10:20
Osaka Josho Gakuen Osaka Center In-situ Evaluation of Vth and AC Gain of 90 nm CMOS Differential Pair Transistors
Yoji Bando, Satoshi Takaya, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2010-23
 [more] ICD2010-23
pp.11-14
ICD 2009-12-14
13:30
Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] Simulation of Substrate Noise Impact on CMOS Analog Circuit
Satoshi Takaya, Yoji Bando, Makoto Nagata (Kobe Univ.) ICD2009-81
We have measured and simulated substrate noise impact on basic analog amplifier using 90-nm CMOS test chip. To measure s... [more] ICD2009-81
pp.31-34
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