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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SIP, CAS, MSS, VLD | 2017-06-20 15:30 |
Niigata | Niigata University, Ikarashi Campus | Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit Yuta Ukon, Shimpei Sato, Atsushi Takahashi (Tokyo Inst. of Tech.)  CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23 |
There are a lot of high load processing that is not required high accuracy at the data center. An approximate computing ... [more] | CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23 pp.119-124 |
| VLD, IPSJ-SLDM | 2017-05-10 16:05 |
Fukuoka | Kitakyushu International Conference Center | [Invited Talk]
Launch of IEEE CEDA All Japan Joint Chapter and Its Role Atsushi Takahashi (Tokyo Tech) VLD2017-3 |
IEEE the Council on Electronic Design Automation (CEDA) All Japan Joint Chapter (AJJC) was founded in 2014. In this manu... [more] | VLD2017-3 pp.13-16 |
| VLD | 2017-03-02 10:30 |
Okinawa | Okinawa Seinen Kaikan | High-speed TPL Layout Decomposition Method based on Positive Semidefinite Relaxation using Polygon Clustering Shohei Handa, Shimpei Sato, Atsushi Takahashi (Tokyo TECH) VLD2016-111 |
[more] | VLD2016-111 pp.55-60 |
| VLD | 2017-03-02 11:20 |
Okinawa | Okinawa Seinen Kaikan | Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning Atsushi Ogashira, Shimpei Sato, Atsushi Takahashi (Tokyo TECH) VLD2016-113 |
In current semiconductor design, high quality and short time design is required. In an advanced lithography technology... [more] |
VLD2016-113 pp.67-72 |
| VLD | 2017-03-02 11:45 |
Okinawa | Okinawa Seinen Kaikan | Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing Shun Sugihara, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2016-114 |
In printed circuit board, to meet requirements such as delay and noise, routing of each net is necessary to achieve its... [more] |
VLD2016-114 pp.73-78 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 09:25 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit Shimpei Sato, Yuta Ukon, Atsushi Takahashi (Tokyo TECH) VLD2016-95 CPSY2016-131 RECONF2016-76 |
When variable latency for digital circuits are assumed, circuits can work with a small clock period that has the possib... [more] |
VLD2016-95 CPSY2016-131 RECONF2016-76 pp.165-170 |
| MBE, NC (Joint) |
2016-03-22 10:55 |
Tokyo | Tamagawa University | Attempt of high frequency blocking in surface electrical stimulation Atsushi Takahashi, Ryoko Futami (Fukushima Uni.) MBE2015-106 |
Two experiments to develop a new selective nerve stimulation method were performed. In the first experiment, we used tw... [more] |
MBE2015-106 pp.17-20 |
| VLD | 2016-03-02 10:30 |
Okinawa | Okinawa Seinen Kaikan | Self-Aligned Quadruple Patterning-Aware Three-Color Grid Routing with Different Color Net Toshiyuki Hongo, Atsushi Takahashi (Tokyo Tech) VLD2015-135 |
Self-Aligned Quadruple Patterning (SAQP) is an important manufacturing technique for sub 14 nm technology node. In this... [more] |
VLD2015-135 pp.137-142 |
| VLD | 2016-03-02 13:50 |
Okinawa | Okinawa Seinen Kaikan | Acceleration of General Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection Hiroshi Nakatsuka, Atsushi Takahashi (Tokyo Tech) VLD2015-140 |
General synchronous circuits are proposed as having taken the place of complete synchronous circuits and do not necessar... [more] | VLD2015-140 pp.167-172 |
| MSS, CAS, SIP, VLD | 2015-06-17 16:20 |
Hokkaido | Otaru University of Commerce | [Panel Discussion]
The Role of System and Signal Processing Subsociety
-- Society Activity and Job Search -- Atsushi Takahashi (Tokyo Tech), Yoshihiro Kaneko (Gifu Univ.), Yusuke Matsunaga (Kyushu Univ.), Osamu Hoshuyama, Yuichi Nakamura (NEC) CAS2015-12 VLD2015-19 SIP2015-43 MSS2015-12 |
The four technical committees of System and Signal Processing Subsociety have been holding joint workshop since 2010. We... [more] | CAS2015-12 VLD2015-19 SIP2015-43 MSS2015-12 p.65 |
| VLD, IPSJ-SLDM | 2015-05-14 10:05 |
Fukuoka | Kitakyushu International Conference Center | NP-completeness of Routing Problem with Bend Constraint Toshiyuki Hongo, Atsushi Takahashi (Tokyo Tech) VLD2015-3 |
Self-Aligned Quadruple Patterning (SAQP) in which side-wall process is repeated twice is an important manufacturing tech... [more] | VLD2015-3 pp.13-18 |
| VLD | 2015-03-02 13:25 |
Okinawa | Okinawa Seinen Kaikan | A cut-pattern reduction method for routing in Self-Aligned Double Patterning Noriyuki Takahashi, Takeshi Ihara, Atsushi Takahashi (Tokyo Tech) VLD2014-154 |
In Self-Aligned Double Patterning (SADP), a routing method that generates a SADP friendly routing pattern efficiently ... [more] |
VLD2014-154 pp.7-12 |
| VLD | 2015-03-04 13:00 |
Okinawa | Okinawa Seinen Kaikan | An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework Satoshi Ohtsuki, Atsushi Takahashi (Tokyo Tech) VLD2014-181 |
In the current typical of integrated circuits, the performance is determined by the maximum delay between flip-flops. Th... [more] | VLD2014-181 pp.159-164 |
| ICD, SDM | 2014-08-04 13:55 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
STT-MRAM Development for Embedded Cache Memory Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LEAP) SDM2014-68 ICD2014-37 |
We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration ... [more] | SDM2014-68 ICD2014-37 pp.35-38 |
| VLD, IPSJ-SLDM | 2014-05-29 11:30 |
Fukuoka | Kitakyushu International Conference Center | LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba) VLD2014-6 |
One of the most promising techniques in the 14 nm logic node and beyond is triple patterning lithography (TPL). Recently... [more] | VLD2014-6 pp.27-32 |
| VLD | 2014-03-04 09:15 |
Okinawa | Okinawa Seinen Kaikan | An Enhancement of Length Difference Reduction Algorithm for Set Pair Routing Yusaku Yamamoto, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2013-142 |
Recent advances in circuit speed force to realize signal propagation delay accurately. In PCB routing design, desired... [more] |
VLD2013-142 pp.49-54 |
| VLD | 2014-03-04 13:50 |
Okinawa | Okinawa Seinen Kaikan | Local Pattern Modification Method for Lithographical ECO in Double Patterning Yutaro Miyabe, Atsushi Takahashi, Tomomi Matsui (Tokyo Inst. of Tech.), Yukihide Kohira (Univ. of Aizu), Yoko Yokoyama (Toshiba) VLD2013-149 |
In advanced semiconductor manufacturing processes, even though a pattern is generated according to a design rule, hot s... [more] |
VLD2013-149 pp.87-92 |
| VLD | 2014-03-04 14:15 |
Okinawa | Okinawa Seinen Kaikan | Self-Aligned Double Patterning-Aware Modified Two-color Grid Routing Takeshi Ihara, Atsushi Takahashi (Tokyo Inst. of Tech.), Chikaaki Kodama (TOSHIBA) VLD2013-150 |
[more] | VLD2013-150 pp.93-98 |
| ICD | 2013-04-11 09:50 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Talk]
A Novel MTJ for STT-MRAM with a Dummy Free Layer and Dual Tunnel Junctions Koji Tsunoda, Hideyuki Noshiro, Chikako Yoshida, Yuuichi Yamazaki, Atsushi Takahashi, Yoshihisa Iba, Akiyoshi Hatada, Masaaki Nakabayashi, Takashi Takenaga, Masaki Aoki, Toshihiro Sugii (LEAP) ICD2013-2 |
A novel magnetic tunnel junction (MTJ) for embedded memory applications such as spin transfer torque magneto-resistive r... [more] | ICD2013-2 pp.5-10 |
| ICD | 2012-12-17 13:30 |
Tokyo | Tokyo Tech Front | [Invited Talk]
High-performance STT-MRAM and Its Integration for Embedded Application Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LESP) ICD2012-90 |
High-performance spin transfer torque MRAM (STT-MRAM) for embedded cache memories was developed, utilizing a top-pinned ... [more] | ICD2012-90 pp.17-20 |
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