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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CAS, NLP |
2021-10-14 15:50 |
Online |
Online |
Implementation of a Generative Adversarial Network as Bitwise Neural Network Takuma Matsuno, Gauthier Lovic (Ariake College) CAS2021-28 NLP2021-26 |
Generative Adversarial Network (GAN) is an artificial intelligence algorithm in which a generative network, which produc... [more] |
CAS2021-28 NLP2021-26 pp.62-67 |
CAS, NLP |
2021-10-14 16:15 |
Online |
Online |
Implementation and evaluation of a FM synthesis circuit using HDLRuby Aito Fukunaga, Gauthier Lovic (NITAC) CAS2021-29 NLP2021-27 |
[more] |
CAS2021-29 NLP2021-27 pp.68-73 |
CAS, ICTSSL |
2021-01-28 17:15 |
Online |
Online |
A Hardware Implementation of Neural Networks using HDLRuby, a Ruby-based Hardware Description Language Ryota Sakai, Yuki Maehara, Lovic Gauthier (NITAC) CAS2020-53 ICTSSL2020-38 |
In the recent years, FPGAs have been attracting attention as neural network accelerators for their superior performance ... [more] |
CAS2020-53 ICTSSL2020-38 pp.79-84 |
CAS, ICTSSL |
2021-01-28 17:35 |
Online |
Online |
Study of a Hardware Implementation of a Long Short-Term Memory with HDLRuby Yuki Maehara, Ryota Sakai, Lovic Gauthier (NITAC) CAS2020-54 ICTSSL2020-39 |
In the recent years, many global companies have attempted to use FPGA for implementing applications in the field of AI s... [more] |
CAS2020-54 ICTSSL2020-39 pp.85-90 |
IE, SIP, ICD, VLD, IPSJ-SLDM [detail] |
2012-10-19 13:00 |
Iwate |
Hotel Ruiz |
Accelerator Architecture for Multi Scale Filter Operation Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 |
Image recognition processing includes a number of filter operations
which dominate the total execution time. Exploiting... [more] |
VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 pp.59-64 |
ICD, IE, SIP, IPSJ-SLDM [detail] |
2011-10-24 14:20 |
Miyagi |
Ichinobo(Sendai) |
Three-Dimensional Accelerator Architecture for Image Recognition Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) SIP2011-63 ICD2011-66 IE2011-62 |
Image recognition used widely in several areas needs high-performance and low power processor. Accelerator is an effecti... [more] |
SIP2011-63 ICD2011-66 IE2011-62 pp.7-12 |
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