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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2018-01-30
13:30		 Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Lateral Charge Migration Suppression Technique of 3D-NAND Flash by Vth Nearing
Kyoji Mizoguchi, Shohei Kotaki, Yoshiaki Deguchi, Ken Takeuchi (Chuo Univ.) SDM2017-93		 In the near data computing, a SSD controller embeds more processing units and RAMs to execute a part of application whic... [more] SDM2017-93
pp.9-12
DC, SS 2016-10-27
13:40		 Shiga Hikone Kinro-Fukushi Kaikan Bldg. Single Limited-Magnitude Error Correcting Codes Using Integer Residue Ring of Large Order
Shohei Kotaki, Masato Kitakami (Chiba Univ.) SS2016-22 DC2016-24		 Multilevel memories, which store multiple bit information within a memory cell,
cause specific errors which mostly shif... [more]		 SS2016-22 DC2016-24
pp.25-29
DC 2013-10-24
15:25		 Tokyo Kikai-Shinko-Kaikan Bldg. A Class of q-Ary Unidirectional Error Correcting Codes for MLC NAND Flash Memories
Shohei Kotaki, Masato Kitakami (Chiba Univ.) DC2013-25		 Error correcting codes (ECCs) are essential techniques to ensure reliability of NAND Flash Memories. As typical error so... [more] DC2013-25
pp.25-30
DC 2011-10-20
13:30		 Tokyo   Neighborhood Level Error Control Codes for Multiple-level Systems
Shohei Kotaki, Masato Kitakami (Chiba Univ.) DC2011-23		 Multiple-level concept, which deals with more than 2 states as data unit, is used in such systems as Flash Memory or mod... [more] DC2011-23
pp.19-24
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