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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2019-02-28 14:55 |
Okinawa | Okinawa Ken Seinen Kaikan | [Memorial Lecture]
Methods for Reducing Power and Area of BDD-based Optical Logic Circuits Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.), Akihiko Shinya, Masaya Notomi (NTT)  VLD2018-116 HWS2018-79 |
[more] | VLD2018-116 HWS2018-79 pp.139-144 |
| CAS, CS | 2017-02-23 16:05 |
Shiga | [Invited Talk]
CMOS Optical Receiver for High Density and High Speed Optical Interconnection Akira Tsuchiya, Takuya Nakao (Kyoto Unv.), Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka (NTT), Hidetoshi Onodera (Kyoto Unv.) CAS2016-124 CS2016-85 |
[more] | CAS2016-124 CS2016-85 pp.59-62 |
|
| SDM | 2017-02-06 14:10 |
Tokyo | Tokyo Univ. | [Invited Talk]
Large Scale Crossbar Switch Block (CSB) with Via-Switch for a Low-Power FPGA Naoki Banno, Munehiro Tada, Koichiro Okamoto, Noriyuki Iguchi, Toshitsugu Sakamoto, Hiromitsu Hada (NEC Corp.), Hiroyuki Ochi (Ritsumeikan Univ.), Hidetoshi Onodera (Kyoto Univ.), Masanori Hashimoto (Osaka Univ.), Tadahiko Sugibayashi (NEC Corp.) SDM2016-144 |
[more] | SDM2016-144 pp.29-34 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 15:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process Michitarou Yabuuchi, Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Jun Furuta (KIT), Pieter Weckx (KUL/IMEC), Ben Kaczer (IMEC), Takashi Matsumoto (Univ. of Tokyo), Hidetoshi Onodera (Kyoto Univ.) VLD2016-52 DC2016-46 |
We propose a circuit analysis method using the bimodal RTN (random telegraph noise) model of the defect-centric distri... [more] |
VLD2016-52 DC2016-46 pp.49-54 |
| ICD, MW | 2016-03-04 10:50 |
Hiroshima | Hiroshima University | [Invited Talk]
Design Challenges and Solutions in the era of IoT Hidetoshi Onodera (Kyoto Univ.) MW2015-206 ICD2015-129 |
The talk stars by the exploration of integrated circuits in the era of IoT predicted by empirical laws that have been co... [more] | MW2015-206 ICD2015-129 p.187 |
| ICD, MW | 2016-03-04 15:35 |
Hiroshima | Hiroshima University | Bandwidth Enhancement of Regulated Cascode Transimpedance Amplifier using Inverter Amplifier Stage Masamichi Fujiwara, Akira Tsuchiya (Kyoto Univ.), Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka (NTT), Hidetoshi Onodera (Kyoto Univ.) MW2015-214 ICD2015-137 |
[more] | MW2015-214 ICD2015-137 pp.229-233 |
| VLD | 2016-03-01 17:30 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2015-131 |
A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchrono... [more] | VLD2015-131 p.117 |
| DC, CPSY | 2015-04-17 13:25 |
Tokyo | A study of processor architecture suited for intelligent sensing system Hiroki Hihara, Akira Iwasaki (Univ. of Tokyo), Masanori Hashimoto (Osaka Univ./JST CREST), Hiroyuki Ochi (Rits/JST CREST), Yukio Mitsuyama (KUT/JST CREST), Hidetoshi Onodera (Kyoto Univ./JST CREST), Hiroyuki Kanbara (ASTEM/JST CREST), Kazutoshi Wakabayashi, Takashi Takenaka, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada (NEC/JST CREST) CPSY2015-8 DC2015-8 |
Sensor nodes are now important elements for the system of social infrastructure, and thus intelligent processing capabil... [more] | CPSY2015-8 DC2015-8 pp.43-48 |
|
| VLD | 2015-03-03 15:50 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2014-172 |
Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of micropro... [more] | VLD2014-172 pp.109-114 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 17:40 |
Kanagawa | Hiyoshi Campus, Keio University | Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits Toshihiro Takeshita, Shinichi Nishizawa, AKM Mahfuzul Islam, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ) VLD2014-129 CPSY2014-138 RECONF2014-62 |
Simultaneous supply and threshold voltage tuning has a strong impact on the energy reduction of LSI circuits. Therefore,... [more] | VLD2014-129 CPSY2014-138 RECONF2014-62 pp.111-116 |
| VLD | 2014-03-03 13:00 |
Okinawa | Okinawa Seinen Kaikan | Characterization of Random Telegraph Noise using Inhomogeneous Ring Oscillator Shohei Nishimura, Takashi Matsumoto (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) VLD2013-134 |
RTN has severe impact on combinational logic circuits. Extracting accurate (RTN-induced) variation information is a huge... [more] | VLD2013-134 pp.1-6 |
| VLD | 2014-03-03 13:25 |
Okinawa | Okinawa Seinen Kaikan | Impact of CMOS Transistor Random Telegraph Noise on Combinational Circuit Delay Takashi Matsumoto (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) VLD2013-135 |
[more] | VLD2013-135 pp.7-12 |
| VLD | 2014-03-05 10:25 |
Okinawa | Okinawa Seinen Kaikan | Evaluation of Multiple Cell Upsets Considering Parasitic Bipolar Effects Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) VLD2013-157 |
As a result of the process scaling, radiation-induced Multiple Cell Upsets (MCUs) become major issue for LSI reliabilit... [more] |
VLD2013-157 pp.125-130 |
| VLD | 2014-03-05 10:50 |
Okinawa | Okinawa Seinen Kaikan | Analysis of Radiation-Induced Errors in PLL based on Behavioral Modeling SinNyoung Kim (Kyoto Univ.), Tomohiro Fujita (Ritsumeikan Univ.), Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) VLD2013-158 |
This paper presents an analysis of radiation-induced errors in PLL based on behavioral modeling. Radiation strike leads ... [more] | VLD2013-158 pp.131-136 |
| MW | 2013-03-07 13:50 |
Hiroshima | Hiroshima Univ. | [Invited Talk]
Modeling of On-Chip Transmission-Line for Terahertz Integrated Circuit Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) MW2012-176 |
This paper discusses modeling issues of on-chip transmission-line for terahertz integrated circuits. Structure of on-ch... [more] |
MW2012-176 pp.93-96 |
| ICD | 2012-12-18 11:45 |
Tokyo | Tokyo Tech Front | A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop Masaki Masuda, Kanto Kubota, Ryosuke Yamamoto (KIT), Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (KIT), Hidetoshi Onodera (Kyoto Univ.) ICD2012-117 |
We propose a low-power redundant flip-flop to be operated with high reliability over 1 GHz clock frequency based on the ... [more] | ICD2012-117 pp.109-113 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 16:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation Takashi Matsumoto (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hidetoshi Onodera (Kyoto Univ.) VLD2012-70 DC2012-36 |
Designing reliable systems has become more difficult in recent years. In this paper, statistical nature of RTN-induced ... [more] |
VLD2012-70 DC2012-36 pp.63-68 |
| MW | 2011-12-16 14:30 |
Yamaguchi | Yamaguchi University | Effect of Anomalous Skin Effect on Transmission-Line Loss Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) MW2011-139 |
As the progress of technology scaling, the target frequency of high speed integrated circuits has reached over 100GHz. ... [more] |
MW2011-139 pp.77-81 |
| ICD | 2011-12-16 09:55 |
Osaka | A 65-nm Radiation-Hard Flip-Flop Tolerant to Multiple Cell Upsets Ryosuke Yamamoto, Chikara Hamanaka (Kyoto Inst. of Tech.), Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) ICD2011-129 |
MCUs in redundant FFs is a dominant factor in a current deep-submicron process. A layout structure to avoid MCUs is prop... [more] | ICD2011-129 pp.131-136 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 15:05 |
Miyazaki | NewWelCity Miyazaki | Multi-core LSI Lifetime Extension by NBTI-Recovery-based Self-healing Takashi Matsumoto, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hidetoshi Onodera (Kyoto Univ.) CPM2011-160 ICD2011-92 |
Designing reliable systrems has become more difficult in recent years. Negative-Bias-Temperature-In-stability (NBTI) is ... [more] | CPM2011-160 ICD2011-92 pp.59-63 |
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