Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC |
2022-03-01 14:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
SAT-based LFSR Seed Generation for Delay Fault BIST Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.) DC2021-74 |
So far, a one-pass LFSR seed generation method for delay fault BIST has been proposed. The method directly generates see... [more] |
DC2021-74 pp.57-62 |
DC |
2020-12-11 15:05 |
Hyogo |
(Primary: On-site, Secondary: Online) |
Vibration Measurement of Signal Bonds for Automatic Train Control Yuki Echigo, Satoshi Ohtake (Oita Univ.) DC2020-65 |
[more] |
DC2020-65 pp.33-38 |
DC |
2020-02-26 10:25 |
Tokyo |
|
Defective Chip Prediction Modeling Using Convolutional Neural Networks Ryunosuke Oka, Satoshi Ohtake (Oita Univ.), Kouichi Kumaki (Renesas) DC2019-87 |
In recent years, the cost of LSI testing which guarantees reliability has relatively increased due to the development of... [more] |
DC2019-87 pp.7-12 |
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 15:45 |
Ehime |
Ehime Prefecture Gender Equality Center |
Compacted Seed Generation for Built-in Self-Diagnosis of Delay Faults Yuta Nakano, Satoshi Ohtake (Oita Univ.) VLD2019-44 DC2019-68 |
[more] |
VLD2019-44 DC2019-68 pp.139-143 |
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 16:35 |
Ehime |
Ehime Prefecture Gender Equality Center |
Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths Suguru Rikino, Yushiro Hiramoto, Satoshi Ohtake (Oita Univ.) VLD2019-46 DC2019-70 |
Hardware Trojan detection is important to ensure security of LSIs.
If a hardware Trojan is inserted in a signal line o... [more] |
VLD2019-46 DC2019-70 pp.151-155 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:30 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST Kyonosuke Watanabe, Satoshi Ohtake (Oita Univ.) VLD2017-35 DC2017-41 |
With the miniaturization and high speed of large scale integrated circuits, it has become important to test delay faults... [more] |
VLD2017-35 DC2017-41 pp.49-54 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:55 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas Electronics) VLD2017-36 DC2017-42 |
Today, semiconductor technologies have developed and advance the integration density of LSI circuits.
A technique which... [more] |
VLD2017-36 DC2017-42 pp.55-60 |
DC |
2017-02-21 11:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Built-In Self Diagnosis Architecture for Logic Design Keisuke Kagawa, Fumiya Yano, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Satoshi Ohtake (Oita Univ.) DC2016-76 |
Recently, roles of automotive LSI to realize a functional safety of vehicle are increasing. In order to guarantee the fu... [more] |
DC2016-76 pp.11-16 |
DC |
2017-02-21 12:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design) DC2016-77 |
Today, advancements of semiconductor technology have progress to high integration of LSI circuits.
A technique which ke... [more] |
DC2016-77 pp.17-22 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:10 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
An approach to LFSR/MISR seed generation for delay fault BIST Daichi Shimazu, Satishi Ohtake (Oita Univ.) VLD2015-70 DC2015-66 |
In this paper, we propose a method of LFSR/MISR seed generation for delay fault BIST.
A widely used conventional way to... [more] |
VLD2015-70 DC2015-66 pp.213-218 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:35 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
Design of BIST with soft error resilience for testing FPGAs Hiroki Ueda, Daichi Shimadu, Satoshi Ohtake (Oita univ.) VLD2015-71 DC2015-67 |
[more] |
VLD2015-71 DC2015-67 pp.219-224 |
DC |
2015-02-13 15:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg |
A Method of LFSR Seed Generation for Hierarchical BIST Kosuke Sawaki, Satoshi Ohtake (Oita Univ.) DC2014-85 |
A linear feedback shift register (LFSR) is used as a test pattern generator of built-in self-test (BIST).
In BIST, alth... [more] |
DC2014-85 pp.43-48 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:10 |
Oita |
B-ConPlaza |
A Method of Burn-in Fail Prediction of LSIs Based on Supervised Learning Using Cluster Analysis Shogo Tetsukawa, Seiya Miyamoto, Satoshi Ohtake (Oita Univ.), Yoshiyuki Nakamura (Renesas) VLD2014-110 DC2014-64 |
Production test of LSIs consists of several test phases such as wafer test phase, package test phase, burn-in test phase... [more] |
VLD2014-110 DC2014-64 pp.251-256 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 08:55 |
Kagoshima |
|
A Method of LFSR Seed Generation for Delay Fault BIST Taro Honda, Satoshi Ohtake (Oita Univ.) VLD2013-92 DC2013-58 |
In this paper, we propose a method to generate LFSR seeds for delay fault BIST. A conventional way to generate seeds is ... [more] |
VLD2013-92 DC2013-58 pp.227-231 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 09:45 |
Kagoshima |
|
A Method of High Quality Transition Test Generation Using RTL Information Hiroyuki Nakashima, Satoshi Ohtake (Oita Univ.) VLD2013-94 DC2013-60 |
With the miniaturization and high speed of large scale integrated circuits (VLSIs), it has become important to test dela... [more] |
VLD2013-94 DC2013-60 pp.239-244 |
DC |
2013-06-21 14:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A method of deterministic LFSR seed generation for scan-based BIST Takanori Moriyasu, Satoshi Ohtake (Oita Univ.) DC2013-11 |
This paper proposes a method of LFSR seed generation for LFSR reseeding of scan-based BIST of VLSI circuits. So far, a s... [more] |
DC2013-11 pp.7-12 |
DC |
2012-02-13 14:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Test Generation Method for Synchronously Designed QDI Circuits Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) DC2011-83 |
Quasi-Delay-Insensitive(QDI) design has been attracting attention as one of the practical techniques for implementation ... [more] |
DC2011-83 pp.43-48 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 11:20 |
Miyazaki |
NewWelCity Miyazaki |
A Method of Thermal Uniformity Control During BIST Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) VLD2011-86 DC2011-62 |
Along with the improvement in semiconductor technology, it is important to ensure product quality that small delay defec... [more] |
VLD2011-86 DC2011-62 pp.197-202 |
ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas |
Ho Chi Minh City University of Technology |
[Invited Talk]
Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.) |
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are takin... [more] |
|
DC |
2010-06-25 13:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2010-8 |
Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput... [more] |
DC2010-8 pp.1-6 |