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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, CPSY | 2015-12-18 13:30 |
Kyoto | Kyoto Institute of Technology | Power optimization based on a simple power model for a micro-controller Hayate Okuhara, Yu Fujita, Kuniaki Kitamori (Keio Univ.), Kimiyoshi Usami (Shibaura Institute of Tech.), Hideharu Amano (Keio Univ.)  ICD2015-88 CPSY2015-101 |
[more] | ICD2015-88 CPSY2015-101 pp.93-98 |
| VLD | 2015-03-04 09:40 |
Okinawa | Okinawa Seinen Kaikan | Ground Bounce Suppressive Effect using Power Switch Driver to control Power Switch Rise Time Tetsutaro Ohnishi, Kimiyoshi Usami (S.I.T.) VLD2014-176 |
While Power Gating technology enables us to reduce leakage current, it causes a serious problem of occurring Ground Boun... [more] | VLD2014-176 pp.129-134 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:15 |
Oita | B-ConPlaza | Design of Flip-Flop with Timing Error Tolerance Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33 |
Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the ci... [more] | VLD2014-79 DC2014-33 pp.45-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita | B-ConPlaza | High speed design of sub-threshold circuit by using DTMOS Yuji Fukudome, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech), Masao Yanagisawa (Waseda Univ.) VLD2014-88 DC2014-42 |
Low power consumption is achieved by operating circuits in sub-threshold region. However, in sub-threshold region, the... [more] |
VLD2014-88 DC2014-42 pp.117-121 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita | B-ConPlaza | Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56 |
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] | VLD2014-102 DC2014-56 pp.203-208 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-02 13:25 |
Miyagi | Local pulse generation in variable stages pipeline designs for low energy consumption Takayuki Nii, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Univ.), Masao Yanagisawa (Waseda Univ.) VLD2014-61 ICD2014-54 IE2014-40 |
The increase of energy consumption due to improved performance has become a problem in the mobile terminal, and various ... [more] | VLD2014-61 ICD2014-54 IE2014-40 pp.7-12 |
|
| ICD, SDM | 2014-08-04 09:00 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology Koichiro Ishibashi (UEC), Nobuyuki Sugii (LEAP), Kimiyoshi Usami (SIT), Hideharu Amano (KU), Kazutoshi Kobayashi (KIT), Cong-Kha Pham (UEC), Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita (LEAP) SDM2014-62 ICD2014-31 |
[more] | SDM2014-62 ICD2014-31 pp.1-4 |
| CPSY, DC (Joint) |
2014-07-30 18:15 |
Niigata | Toki Messe, Niigata | Design of OpenCL Library and Execution Dispatcher for Embedded Accelerator Ryuichi Sakamoto, Mikiko Sato (Tokyo Univ. of Agriculture and Tech. (TUAT)), Hideharu Amano, Tadahiro Kuroda (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hiroshi Nakamura (Univ. of Tokyo), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech. (TUAT)) CPSY2014-46 |
Recently, an embedded processor for use in smartphones and other devices is equipped with some power-efficient accelerat... [more] | CPSY2014-46 pp.215-220 |
| VLD | 2014-03-05 13:00 |
Okinawa | Okinawa Seinen Kaikan | Investigation of thermal monitor for applying to Dynamic Voltage Scaling in SOTB Tatsuya Wada, Kimiyoshi Usami (Shibaura Inst. of Tech) VLD2013-160 |
SOTB (Silicon on Thin Buried Oxide) transistors can operate at high speed in the ultra-low voltage. However, variation i... [more] | VLD2013-160 pp.141-146 |
| VLD | 2014-03-05 13:25 |
Okinawa | Okinawa Seinen Kaikan | Experiment and Analysis on Temperature Dependence of Delay and Energy for Subthreshold Circuits Hiroki Kushida, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Masao Yanagisawa (Waseda Univ.) VLD2013-161 |
Low voltage design has been used in order to reduce the energy dissipation of mobile network equipment. However, as supp... [more] | VLD2013-161 pp.147-151 |
| VLD | 2014-03-05 13:50 |
Okinawa | Okinawa Seinen Kaikan | Design methodology on Dynamic Multi-Vth control technique for Silicon on Thin Buried Oxide(SOTB) Tatsuki Saigusa, Kimiyoshi Usami (Shibaura Inst. of Tech) VLD2013-162 |
Silicon on thin BOX(SOTB) is one of FD-SOI device.It is possible to operate with ultra-low voltage of 0.4V and greatly c... [more] | VLD2013-162 pp.153-158 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 15:40 |
Kanagawa | Hiyoshi Campus, Keio University | Methodology for NBTI measurement using an on-chip leakage monitor circuit Takaaki Sato, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2013-131 CPSY2013-102 RECONF2013-85 |
Miniaturization in recent years ,LSI's aging has become prominent as a factor that prevents the normal operation.By meas... [more] | VLD2013-131 CPSY2013-102 RECONF2013-85 pp.173-178 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:25 |
Kagoshima | Development of a fine-grain power-gated CPU "Geyser-3" and adaptive power-off control to the temperature Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Inst. of Tech.), Weihan Wang, Hideharu Amano (Keio Univ), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Univ of Agriculture and Tech), Masaaki Kondo (Univ of Elec-Comm), Hiroshi Nakamura (Univ of Tokyo) VLD2013-80 DC2013-46 |
[more] | VLD2013-80 DC2013-46 pp.135-140 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 11:40 |
Kagoshima | Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-97 DC2013-63 |
In this paper, we propose a clock energy-efficient high-level synthesis algorithm for HDR-mcd architecture. In HDR-mcd,... [more] |
VLD2013-97 DC2013-63 pp.263-268 |
|
| VLD | 2013-03-06 10:55 |
Okinawa | Okinawa Seinen Kaikan | Design and Evalution of Sleep Control Circuit for Fine-grain Power Gating Yoshihiro Tsurui, Kimiyoshi Usami, Tatsunori Hashida, Tetsuya Muto, Yuki Shimada (Shibaura Inst. of Tech.) VLD2012-155 |
In order to perform more efficient Fine-grain Power Gating which reduces the leakage power by cutting Power Supply, it i... [more] | VLD2012-155 pp.105-110 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 15:00 |
Kanagawa | Automatic generation of the Power-Switch Driver Circuit and evaluation in Power-gating design implementation Makoto Miyauchi, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2012-116 CPSY2012-65 RECONF2012-70 |
[more] | VLD2012-116 CPSY2012-65 RECONF2012-70 pp.51-56 |
|
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 16:00 |
Kanagawa | Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) VLD2012-118 CPSY2012-67 RECONF2012-72 |
Run-time Power Gating (RTPG) reduces leakage energy by turning off a power switch(PS) for idle periods of a circuit duri... [more] | VLD2012-118 CPSY2012-67 RECONF2012-72 pp.63-68 |
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| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 17:00 |
Kanagawa | Dynamic Multi-Vth Control Using Body Biasing in Silicon on Thin Buried Oxide (SOTB) Shinya Ajiro, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2012-120 CPSY2012-69 RECONF2012-74 |
Silicon on thin BOX(SOTB) is an FD-SOI device being possible to operate with ultra-low voltage of 0.4V and greatly chang... [more] | VLD2012-120 CPSY2012-69 RECONF2012-74 pp.75-80 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Analytical model of energy dissipation for comparing adder architectures Nao Konishi, Kimiyoshi Usami (Shibaura I.T.) VLD2012-80 DC2012-46 |
This paper describes analytical models for delay and energy dissipation of ripple-carry, carry look-ahead, and parallel ... [more] | VLD2012-80 DC2012-46 pp.123-128 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 14:15 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | SAAV : Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology Univ./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-82 DC2012-48 |
An adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multip... [more] | VLD2012-82 DC2012-48 pp.135-140 |
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