IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-24
09:55
Online Online Study on Reverse Converters for RNS moduli set {2^k,2^n+1,2^n-1} using Signed-Digit numbers
Takahiro Morii, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2021-50 CPSY2021-19 RECONF2021-58
In this study, we propose reverse converters for moduli set ${2^k,2^n+1,2^n-1}$ that convert residue number system to we... [more] VLD2021-50 CPSY2021-19 RECONF2021-58
pp.7-12
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-18
13:25
Kanagawa Raiosha, Hiyoshi Campus, Keio University Residue-weighted number conversion based on Signed-Digit arithmetic for a four moduli set
Kouhei Yamazaki, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2017-69 CPSY2017-113 RECONF2017-57
 [more] VLD2017-69 CPSY2017-113 RECONF2017-57
pp.43-48
CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] 2017-01-24
17:20
Kanagawa Hiyoshi Campus, Keio Univ. A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption
Kazumasa Ishikawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2016-92 CPSY2016-128 RECONF2016-73
In this paper, we presented a new residue addition algorithm using Signed-Digit (SD) numbers for the applications such a... [more] VLD2016-92 CPSY2016-128 RECONF2016-73
pp.147-152
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
14:10
Kanagawa   Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number
Takuya Kobayashi, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2012-114 CPSY2012-63 RECONF2012-68
Signed-Digit (SD) has a redundancy by using \{-1,0,1\}.
By applying the redundant binary representation to arithmetic c... [more]
VLD2012-114 CPSY2012-63 RECONF2012-68
pp.39-44
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
14:35
Kanagawa   Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic
Junichi Asaoka, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2012-115 CPSY2012-64 RECONF2012-69
RSA encryption processing spends a lot of time on modular exponentiation of long word length, therefore the speed of the... [more] VLD2012-115 CPSY2012-64 RECONF2012-69
pp.45-50
 Results 1 - 5 of 5  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan