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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, IPSJ-ARC | 2012-01-19 11:40 |
Tokyo | [Invited Talk]
Low Power Technologies and Scaling Law Toward Future Koichiro Ishibashi (UEC-Tokyo)  ICD2011-136 |
LSI density has been increasing by Moore's law, and performance of LSI has also been increasing with decreasing power di... [more] | ICD2011-136 pp.21-22 |
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| ICD, ITE-IST | 2011-07-22 09:50 |
Hiroshima | Hiroshima Institute of Technology | On-Chip Resonant Supply Noise Reduction Using Active Decoupling Capacitors Jinmyoung Kim (Tokyo Univ.), Toru Nakura (VDEC), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (VDEC) ICD2011-27 |
[more] | ICD2011-27 pp.69-72 |
| ICD, SDM | 2010-08-26 09:10 |
Hokkaido | Sapporo Center for Gender Equality | On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks Jinmyoung Kim, Toru Nakura (Univ. of Tokyo.), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) SDM2010-124 ICD2010-39 |
This paper proposes an on-chip supply resonance noise reduction method for multi-IP cores utilizing parasitic capacitanc... [more] | SDM2010-124 ICD2010-39 pp.1-4 |
| ICD, SDM | 2007-08-23 15:25 |
Hokkaido | Kitami Institute of Technology | A 1.92us-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors Kazuki Fukuoka, Osamu Ozawa, Ryo Mori, Yasuto Igarashi, Toshio Sasaki, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi (Renesas Technology) SDM2007-153 ICD2007-81 |
A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing t... [more] | SDM2007-153 ICD2007-81 pp.69-73 |
| ICD | 2007-04-13 09:40 |
Oita | [Invited Talk]
A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) ICD2007-11 |
We propose a Wafer Level Burn-In (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair s... [more] | ICD2007-11 pp.59-64 |
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| ICD, ITE-CE | 2006-12-15 11:15 |
Hiroshima | Low Power SOC Design using Partial-Trench-Isolation ABC SOI for sub-100-nm LSTP technology Osamu Ozawa, Kazuki Fukuoka, Yasuto Igarashi, Takashi Kuraishi, Yoshihiko Yasu, Yukio Maki, Takashi Ipposhi, Toshihiko Ochiai, Masayoshi Shirahata, Koichiro Ishibashi (Renesas) |
[more] | ICD2006-163 pp.115-119 |
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| ICD, SDM | 2006-08-18 12:05 |
Hokkaido | Hokkaido University | A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stabi... [more] | SDM2006-148 ICD2006-102 pp.133-136 |
| ICD, SDM | 2006-08-18 14:35 |
Hokkaido | Hokkaido University | A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits Makoto Yabuuchi, Shigeki Ohbayashi, Koji Nii, Yasumasa Tsukamoto (Renesas Technology), Susumu Imaoka (Renesas Design), Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Hiroshi Makino, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] | SDM2006-151 ICD2006-105 pp.149-153 |
| ICD | 2006-04-14 13:50 |
Oita | Oita University | Worst-Case Ananlysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth Variability Yasumasa Tsukamoto, Koji Nii (Renesas Technology), Susumu Imaoka (Renesas Design), Yuji Oda (Shikino High-Tech.), Shigeki Ohbayashi, Makoto Yabuuchi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] | ICD2006-18 pp.97-102 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-21 09:20 |
Miyagi | Ichinobo, Sakunami-Spa | Substrate Noise Reduction and Random Variability Neutralization with Self Adjusted Forward Body Bias Control Yoshihide Komatsu, Koichiro Ishibashi, Toshiro Tsukada, Masaharu Yamamoto (STARC), Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata (Kobe Univ.) |
[more] | SIP2005-116 ICD2005-135 IE2005-80 pp.7-12 |
| ICD, SDM | 2005-08-19 13:25 |
Hokkaido | HAKODATE KOKUSAI HOTEL | 0.5V Asymmetric Three-Tr. Cell (ATC) DRAM Using 90nm Generic CMOS Logic Process Motoi Ichihashi, Haruki Toda, Yasuo Itoh, Koichiro Ishibashi (STARC) |
Asymmetric Three-Tr. Cell (ATC) DRAM which has one P- and two N-MOS transistors for one unit cell is proposed with "forc... [more] | SDM2005-151 ICD2005-90 pp.49-54 |
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