| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 10:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | hCODE 2.0: An Open-source Platform for FPGA Cluster System Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)  VLD2017-27 DC2017-33 |
In recent years, major cloud providers such as Amazon and Microsoft are improving cloud applications using FPGAs. By in... [more] |
VLD2017-27 DC2017-33 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:25 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | RECONF2017-38 |
Graph processing has memory access with low locality, and it is not easy to process large-scale graphs which have the mi... [more] | RECONF2017-38 pp.7-12 |
| RECONF | 2017-09-26 13:55 |
Tokyo | DWANGO Co., Ltd. | A case study of High-level Synthesis Using Higher-order Function on Functional Language Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-35 |
The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forc... [more] | RECONF2017-35 pp.75-80 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-22 16:20 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | CNN implementation on FPGA with Power of 2 Approximation of Weight Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-6 |
Convolutional Neural Network (CNN), a method of Image recognition, is utilized in various fields. Considering CNN implem... [more] | RECONF2017-6 pp.25-30 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-22 17:10 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | A proposal of Bit Serial Arithmetic Units for Arbitrary Precision Tomonori Miura, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-8 |
In this paper,we propose a bit serial arithmetic unit for arbitrary precision.It calculates 1 digit ev- ery cycle from t... [more] | RECONF2017-8 pp.37-41 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 15:20 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection Futoshi Murase, Daichi Takagi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2016-75 CPSY2016-111 RECONF2016-56 |
We propose a multiple FPGA system using high speed optical serial interconnection for a inter-connection of FPGAs. In th... [more] | VLD2016-75 CPSY2016-111 RECONF2016-56 pp.31-36 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:55 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Development of power estimation tool for three dimensional FPGA Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-46 |
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] | RECONF2016-46 pp.35-40 |
| MSS, CAS, IPSJ-AL [detail] | 2016-11-25 12:55 |
Hyogo | Kobe Institute of Computing | Formal Description of Synchronization by Functional Definition of Synchronous Circuits Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) CAS2016-73 MSS2016-53 |
Synchronous circuits are usually defined as D-Flipflop (D-FF) synchronized circuits, but it is doubtful that D-FF comple... [more] | CAS2016-73 MSS2016-53 pp.99-104 |
| RECONF | 2016-09-06 10:55 |
Toyama | Univ. of Toyama | A Study of Methodology and Tools for Open-source FPGA Accelerators Takuya Nakamichi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-34 |
Today's information and communication society requires more and higher-performance computing devices with the constraint... [more] | RECONF2016-34 pp.45-50 |
| VLD, IPSJ-SLDM | 2016-05-11 13:50 |
Fukuoka | Kitakyushu International Conference Center | Multi bit soft error tolerant FPGA architecture Yuji Nakamura, Takuya Teraoka, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2016-3 |
Due to reaching the nanoscale transistor size, effect of soft error to the memory has become conspicuous. In small devic... [more] | VLD2016-3 pp.35-40 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 11:15 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Study of HW/SW Co-design Framework based on the Virtualization Technology Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2015-52 |
One challenge for the heterogeneous computing with the FPGA is to bridge the development gap between SW and HW design. T... [more] | RECONF2015-52 pp.21-26 |
| RECONF | 2015-09-18 09:25 |
Ehime | Ehime University | Trax solver based on machine-learned evaluation function Takuya Nakamichi, Yusuke Sonoda, Takayuki Matsuzaki, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2015-33 |
We develop a solver of board game Trax. Our basic strategy is a common game tree search algorithm. We explore the best m... [more] | RECONF2015-33 pp.7-12 |
| RECONF | 2015-06-19 12:00 |
Kyoto | Kyoto University | An Area Optimization of 3D FPGA with high speed inter-layer communication link Yuto Takeuchi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-4 |
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] | RECONF2015-4 pp.17-22 |
| RECONF | 2015-06-20 16:15 |
Kyoto | Kyoto University | A Technology Mapping Method for Scalable Logic Module Ryo Araki, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-27 |
In order to implement logic functions, conventional field-programmable gate arrays (FPGAs) employs look-up tables (LUTs)... [more] | RECONF2015-27 pp.147-152 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 11:05 |
Kanagawa | Hiyoshi Campus, Keio University | Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-120 CPSY2014-129 RECONF2014-53 |
The 3D IC technology is being researched to build better performance LSIs in a variety of applications when the process ... [more] | VLD2014-120 CPSY2014-129 RECONF2014-53 pp.41-46 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:45 |
Oita | B-ConPlaza | A hardware description method and sematics providing a timing constrant Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-82 DC2014-36 |
Formal verification methods are wide-spreading due to its mathmatical rigorousaspect, although they limited to synchroun... [more] | VLD2014-82 DC2014-36 pp.81-86 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:00 |
Oita | B-ConPlaza | Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator Takashi Okamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-42 |
The circuit scale of Application Specific Integrated Circuit（ASIC）has been increasing. Therefore the shortening of funct... [more] | RECONF2014-42 pp.45-50 |
| RECONF | 2014-09-18 14:10 |
Hiroshima | Prototype of fault tolerant FPGA using 65nm CMOS process Motoki Amagasaki, Takuya Kajiwara, Kentaro Fujisawa, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-18 |
我々はSoC（System on a Chip）に搭載されるFPGA-IP（Field Programmable Gate Array Intellectual Property）コアに焦点をあてたFT-FPGA（Fault Tolera... [more] |
RECONF2014-18 pp.7-12 |
|
| RECONF | 2014-09-18 14:35 |
Hiroshima | A study of run-time fault detection mechanism for fault-tolerant FPGAs Kentaro Fujisawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-19 |
The fault detection is very important for high reliability system LSI. In this paper, we propose a dynamic fault detecti... [more] | RECONF2014-19 pp.13-18 |
|
| RECONF | 2014-09-19 14:40 |
Hiroshima | Formal Verification System of Multi-clock Synchronous Circuits on Multimodal Logic Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-33 |
Regardless of wide using of a formal verification methods, almost all of the methods limited to single-clock synchrounou... [more] | RECONF2014-33 pp.93-98 |
|
[Return to Top Page]